Inventor

WANG WEI-E

US31 patents

⚠️ This page may combine multiple inventors who share the name “WANG WEI-E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG WEI-E

SAMSUNG ELECTRONICS CO LTD

Horizontal nanosheet FETs and method of manufacturing the same

Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same

Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance

Method of forming multiple-Vt FETs for CMOS circuit applications

Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed

Method of forming internal dielectric spacers for horizontal nanosheet FET architectures

Method of forming multiple-Vt FETS for CMOS circuit applications

Complimentary metal-oxide-semiconductor circuit having transistors with different threshold voltages and method of manufacturing the same

Method of providing source and drain doping for CMOS architecture including FinFET and semiconductor devices so formed

Method of forming multi-threshold voltage devices and devices so formed

Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the same

Methods of forming nanosheets on lattice mismatched substrates

Method of forming multiple-Vt FETS for CMOS circuit applications

Method of forming a thermal shield in a monolithic 3-d integrated circuit

Method of forming multi-threshold voltage devices and devices so formed

Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same

Method of forming isolation dielectrics for stacked field effect transistors (FETs)

Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed

Method of forming a thermal shield in a monolithic 3-D integrated circuit

Metal oxide semiconductor field effect transistor with crystalline oxide layer on a III-V material

Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding

Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same

Interface layer for gate stack using O3 post treatment

Methods of forming defect-free SRB onto lattice-mismatched substrates and defect-free fins on insulators

Method of forming crystalline oxides on III-V materials

WANG WEI-E

Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods

Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device

Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices

Relaxed semiconductor layers with reduced defects and methods of forming the same

OBRADOVIC BORNA J

Multi-layer fin field effect transistor devices and methods of forming the same

WANG GANG

Antiphase domain boundary-free III-V compound semiconductor material on semiconductor substrate and method for manufacturing thereof