Inventor

OBRADOVIC BORNA J

US57 patents

⚠️ This page may combine multiple inventors who share the name “OBRADOVIC BORNA J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OBRADOVIC BORNA J

SAMSUNG ELECTRONICS CO LTD

Horizontal nanosheet FETs and method of manufacturing the same

Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance

Integrated circuit devices including source/drain extension regions and methods of forming the same

Strained stacked nanosheet FETS and/or quantum well stacked nanosheet

Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width

Method and system for performing analog complex vector-matrix multiplication

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

Stacked independently contacted field effect transistor having electrically separated first and second gates

Method of forming internal dielectric spacers for horizontal nanosheet FET architectures

Crystalline multiple-nanosheet III-V channel FETs

Dielectric separation of partial GAA FETs

Structure and method to achieve compressively strained Si NS

High-density neuromorphic computing element

Monolithic multi-bit weight cell for neuromorphic computing

Ferroelectric-based memory cell usable in on-logic chip memory

Method of providing source and drain doping for CMOS architecture including FinFET and semiconductor devices so formed

Selectorless 3D stackable memory

Method of forming multi-threshold voltage devices and devices so formed

Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same

Field effect transistor with decoupled channel and methods of manufacturing the same

Strained stacked nanosheet FETs and/or quantum well stacked nanosheet

Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the same

0T bi-directional memory cell

High-density neuromorphic computing element

High-density neuromorphic computing element

Field effect transistor with decoupled channel and methods of manufacturing the same

Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same

Monolithic multi-bit weight cell for neuromorphic computing

Method of enabling sparse neural networks on memresistive accelerators

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

Method and system for training of neural networks using continuously differentiable models

Method of forming multi-threshold voltage devices and devices so formed

Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same

Low current leakage finFET and methods of making the same

Bi-directional weight cell

Memory device with strong polarization coupling

Method for selectively increasing silicon fin area for vertical field effect transistors

FE-FET-based XNOR cell usable in neuromorphic computing

FinFET with reduced extension resistance and methods of manufacturing the same

Method and system for providing a variation resistant magnetic junction-based XNOR cell usable in neuromorphic computing

High-density neuromorphic computing element

Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same

Field effect transistor with decoupled channel and methods of manufacturing the same

Method for selectively increasing silicon fin area for vertical field effect transistors

OBRADOVIC BORNA J

Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same

Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the same

Multi-layer fin field effect transistor devices and methods of forming the same

Integrated circuit devices including FinFETS and methods of forming the same

ANTONACCI ANTHONY G

Hall effect device having voltage based biasing for temperature compensation

RODDER MARK S

FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same