Inventor

HONG JOON GOO

US46 patents

⚠️ This page may combine multiple inventors who share the name “HONG JOON GOO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HONG JOON GOO

SAMSUNG ELECTRONICS CO LTD

Gate-all-around nanosheet field-effect transistors and methods of manufacturing the same

Semiconductor device having buried power rail

Horizontal nanosheet FETs and method of manufacturing the same

Strained stacked nanosheet FETS and/or quantum well stacked nanosheet

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

Apparatus and method of forming backside buried conductor in integrated circuit

Semiconductor device and method for making the same

Stacked independently contacted field effect transistor having electrically separated first and second gates

Method of forming internal dielectric spacers for horizontal nanosheet FET architectures

Methods of forming semiconductor devices, including forming a metal layer on source/drain regions

Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architectures

Power distribution network using buried power rail

Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

Complimentary metal-oxide-semiconductor circuit having transistors with different threshold voltages and method of manufacturing the same

Method of providing source and drain doping for CMOS architecture including FinFET and semiconductor devices so formed

Method and system for providing a reverse-engineering resistant hardware embedded security module

Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same

Methods for varied strain on nano-scale field effect transistor devices

Method to make self-aligned vertical field effect transistor

0T bi-directional memory cell

Semiconductor cell blocks having non-integer multiple of cell heights

Integrated circuit with buried power rail and methods of manufacturing the same

Method of manufacturing an integrated circuit with buried power rail

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

Apparatus and method of modulating threshold voltage for fin field effect transistor (FinFET) and nanosheet FET

4T4R ternary weight cell with high on/off ratio background

Low current leakage finFET and methods of making the same

Method and system for providing a reverse engineering resistant hardware embedded security module

Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

Method for selectively increasing silicon fin area for vertical field effect transistors

FinFet having dual vertical spacer and method of manufacturing the same

Optimization of sparsified neural network layers for semi-digital crossbar architectures

Variation mitigation scheme for semi-digital mac array with a 2T-2 resistive memory element bitcell

System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs)

FinFET with reduced extension resistance and methods of manufacturing the same

Integrated circuit devices including an element having a non-linear shaped upper surface and methods of forming the same

Method for selectively increasing silicon fin area for vertical field effect transistors

Sacrificial epitaxial gate stressors

Composite piezoelectric capacitor

2T2R binary weight cell with high on/off ratio background

Variation resistant 3T3R binary weight cell with low output current and high on/off ratio

Semiconductor cell blocks having non-integer multiple of cell heights

Nanosheet field effect transistor cell architecture

Methods to achieve strained channel finFET devices

Semiconductor device and method for making the same

KIM MYEONGCHEOL

Semiconductor device and method of forming the same