Inventor · disambiguated record
Mohamed S. Moosa
Also filed as: MOOSA MOHAMED S · MOOSA MOHAMED SULEMAN
15 granted patents·1 pending application·309 citations·filing 1996–2023
92Inventor score
Top patents by PatentIndex Score
16 records- 0194US5822218ASystems, methods and computer program products for prediction of defect-related failures in integrated circuitsUNIV CLEMSON·Filed 1996·Granted Oct 13, 1998·221 cites·73 claims
- 0293US7927989B2Method for forming a transistor having gate dielectric protection and structureFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Apr 19, 2011·27 cites·8 claims
- 0391US7274247B2System, method and program product for well-bias set point adjustmentFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Sep 25, 2007·28 cites·19 claims
- 0486US9553446B2Shared ESD circuitryFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Jan 24, 2017·7 cites·20 claims
- 0584US11862625B2Area-efficient ESD protection inside standard cellsNXP USA INC·Filed 2022·Granted Jan 2, 2024·2 cites·20 claims
- 0682US7279997B2Voltage controlled oscillator with a multiple gate transistor and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Oct 9, 2007·8 cites·14 claims
- 0778US9076656B2Electrostatic discharge (ESD) clamp circuit with high effective holding voltageFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted Jul 7, 2015·5 cites·18 claims
- 0870US7741183B2Method of forming a gate dielectricFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Jun 22, 2010·3 cites·18 claims
- 0965US7215268B1Signal converters with multiple gate devicesFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted May 8, 2007·3 cites·18 claims
- 1062US8330231B2Transistor having gate dielectric protection and structureZHANG DA·Filed 2011·Granted Dec 11, 2012·1 cites·15 claims
- 1158US9478529B2Electrostatic discharge protection systemMILLER JAMES W·Filed 2014·Granted Oct 25, 2016·1 cites·20 claims
- 1258US8254186B2Circuit for verifying the write enable of a one time programmable memoryHOEFLER ALEXANDER B·Filed 2010·Granted Aug 28, 2012·2 cites·20 claims
- 1357US7439791B2Temperature compensation device and method thereofFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Oct 21, 2008·1 cites·14 claims
- 1453US12034000B2Double IO pad cell including electrostatic discharge protection scheme with reduced latch-up riskNXP BV·Filed 2022·Granted Jul 9, 2024·0 cites·20 claims
- 1546US2024364342A1System having single-event latch-up detection and mitigationNXP USA INC·Filed 2023·Application pending·0 cites
- 1642US7612619B2Phase detector device and method thereofFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Nov 3, 2009·0 cites·20 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →