Inventor

BAO RUQIANG

US187 patents

⚠️ This page may combine multiple inventors who share the name “BAO RUQIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAO RUQIANG

IBM

Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions

Dual channel structures with multiple threshold voltages

Leakage control for gate-all-around field-effect transistor devices

Formation of self-aligned bottom spacer for vertical transistors

Integration of super via structure in BEOL

Integration of super via structure in BEOL

Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS

Bottom contact resistance reduction on VFET

Forming a semiconductor structure for reduced negative bias temperature instability

Self-aligned spacer for cut-last transistor fabrication

Threshold voltage modulation through channel length adjustment

Self-aligned semiconductor gate cut

Vertical FET transistor with reduced source/drain contact resistance

Nanosheet FET bottom isolation

Self-aligned top spacers for vertical FETs with in situ solid state doping

Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions

Gate cut in RMG

Oxide isolated fin-type field-effect transistors

Gate cut in RMG

Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device

Conformal replacement gate electrode for short channel devices

Replacement metal gate processes for vertical transport field-effect transistor

VFET metal gate patterning for vertical transport field effect transistor

Enabling low resistance gates and contacts integrated with bilayer dielectrics

Gate-all-around field effect transistor having multiple threshold voltages

Integrated circuit with replacement gate stacks and method of forming same

Vertical transport fin field effect transistors having different channel lengths

Threshold voltage modulation through channel length adjustment

Forming a semiconductor structure for reduced negative bias temperature instability

Low undercut N-P work function metal patterning in nanosheet replacement metal gate process

Self-aligned hybrid substrate stacked gate-all-around transistors

Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner

Enabling anneal for reliability improvement and multi-Vt with interfacial layer regrowth suppression

Contact resistance reduction in nanosheet device structure

Stacked gate structures

Replacement metal gate process for vertical transport field-effect transistor with self-aligned shared contacts

Approach to control over-etching of bottom spacers in vertical fin field effect transistor devices

Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device

Multi-threshold voltage non-planar complementary metal-oxtde-semiconductor devices

Gate to source/drain leakage reduction in nanosheet transistors via inner spacer optimization

Gate first technique in vertical transport FET using doped silicon gates with silicide

Horizontal-trench capacitor

Perpendicular stacked field-effect transistor device

Encapsulation layer for vertical transport field-effect transistor gate stack

Gate-all-around FETs having uniform threshold voltage

Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)

GLOBALFOUNDRIES INC

Metal stack for reduced gate resistance

Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs

Integrated circuit with replacement gate stacks and method of forming same

Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs