Inventor

MOCHIZUKI SHOGO

US276 patents

Patents

50 patents

US10103065B1Oct 16, 2018

Reduction of multi-threshold voltage patterning damage in nanosheet device structure

IBM30 citations94

US10453824B1Oct 22, 2019

Structure and method to form nanosheet devices with bottom isolation

IBM30 citations94

US10276687B1Apr 30, 2019

Formation of self-aligned bottom spacer for vertical transistors

IBM15 citations94

US10243043B2Mar 26, 2019

Self-aligned air gap spacer for nanosheet CMOS devices

IBM16 citations94

US9960272B1May 1, 2018

Bottom contact resistance reduction on VFET

IBM27 citations94

US9954102B1Apr 24, 2018

Vertical field effect transistor with abrupt extensions at a bottom source/drain structure

IBM31 citations94

US9865730B1Jan 9, 2018

VTFET devices utilizing low temperature selective epitaxy

IBM19 citations94

US9805989B1Oct 31, 2017

Sacrificial cap for forming semiconductor contact

IBM29 citations94

US9799765B1Oct 24, 2017

Formation of a bottom source-drain for vertical field-effect transistors

IBM28 citations94

US9773901B1Sep 26, 2017

Bottom spacer formation for vertical transistor

IBM43 citations94

US9773875B1Sep 26, 2017

Fabrication of silicon-germanium fin structure having silicon-rich outer surface

IBM21 citations94

US9748380B1Aug 29, 2017

Vertical transistor including a bottom source/drain region, a gate structure, and an air gap formed between the bottom source/drain region and the gate structure

IBM32 citations94

US9397197B1Jul 19, 2016

Forming wrap-around silicide contact on finFET

IBM28 citations94

US9748382B1Aug 29, 2017

Self aligned top extension formation for vertical transistors

IBM13 citations93

US9704990B1Jul 11, 2017

Vertical FET with strained channel

IBM18 citations93

US9831324B1Nov 28, 2017

Self-aligned inner-spacer replacement process using implantation

IBM14 citations92

US9449921B1Sep 20, 2016

Voidless contact metal structures

IBM17 citations92

US10916638B2Feb 9, 2021

Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance

IBM10 citations86

US10971490B2Apr 6, 2021

Three-dimensional field effect device

IBM6 citations84

US10756175B2Aug 25, 2020

Inner spacer formation and contact resistance reduction in nanosheet transistors

IBM10 citations84

US10600885B2Mar 24, 2020

Vertical fin field effect transistor devices with self-aligned source and drain junctions

IBM8 citations84

US10573521B2Feb 25, 2020

Gate metal patterning to avoid gate stack attack due to excessive wet etching

IBM8 citations84

US10475923B1Nov 12, 2019

Method and structure for forming vertical transistors with various gate lengths

IBM11 citations84

US10461154B1Oct 29, 2019

Bottom isolation for nanosheet transistors on bulk substrate

IBM9 citations84

US10439049B2Oct 8, 2019

Nanosheet device with close source drain proximity

IBM8 citations84

US10388766B2Aug 20, 2019

Vertical transport FET (VFET) with dual top spacer

IBM6 citations84

US10319836B1Jun 11, 2019

Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy

IBM11 citations84

US10312377B2Jun 4, 2019

Localized fin width scaling using a hydrogen anneal

IBM4 citations84

US10096713B1Oct 9, 2018

FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation

IBM7 citations84

US10079299B2Sep 18, 2018

Self aligned top extension formation for vertical transistors

IBM8 citations84

US10008417B1Jun 26, 2018

Vertical transport fin field effect transistors having different channel lengths

IBM11 citations84

US9972682B2May 15, 2018

Low resistance source drain contact formation

IBM13 citations84

US9954103B1Apr 24, 2018

Bottom spacer formation for vertical transistor

IBM11 citations84

US9941391B2Apr 10, 2018

Method of forming vertical transistor having dual bottom spacers

IBM8 citations84

US9923084B2Mar 20, 2018

Forming a fin using double trench epitaxy

IBM4 citations84

US9917060B1Mar 13, 2018

Forming a contact for a semiconductor device

IBM11 citations84

US9911849B2Mar 6, 2018

Transistor and method of forming same

IBM8 citations84

US9754875B1Sep 5, 2017

Designable channel FinFET fuse

IBM14 citations84

US9748359B1Aug 29, 2017

Vertical transistor bottom spacer formation

IBM18 citations84

US9666493B2May 30, 2017

Semiconductor device structure with 110-PFET and 111-NFET curent flow direction

IBM6 citations84

US9595599B1Mar 14, 2017

Dielectric isolated SiGe fin on bulk substrate

IBM9 citations84

US9583599B2Feb 28, 2017

Forming a fin using double trench epitaxy

IBM4 citations84

US9570298B1Feb 14, 2017

Localized elastic strain relaxed buffer

IBM11 citations84

US9390976B2Jul 12, 2016

Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction

IBM8 citations84

US9378952B1Jun 28, 2016

Tall relaxed high percentage silicon germanium fins on insulator

IBM8 citations84

US9059002B2Jun 16, 2015

Non-merged epitaxially grown MOSFET devices

IBM4 citations84

Showing the top 50 of 276 patents by PatentIndex Score.

MOCHIZUKI SHOGO

Patents

Gate metal patterning for tight pitch applications

Self-aligned air gap spacer for nanosheet CMOS devices

High acceptor level doping in silicon germanium

Forming wrap-around silicide contact on finFET

Reduction of multi-threshold voltage patterning damage in nanosheet device structure

Structure and method to form nanosheet devices with bottom isolation

Formation of self-aligned bottom spacer for vertical transistors

Self-aligned air gap spacer for nanosheet CMOS devices

Bottom contact resistance reduction on VFET

Vertical field effect transistor with abrupt extensions at a bottom source/drain structure

VTFET devices utilizing low temperature selective epitaxy

Sacrificial cap for forming semiconductor contact

Formation of a bottom source-drain for vertical field-effect transistors

Bottom spacer formation for vertical transistor

Fabrication of silicon-germanium fin structure having silicon-rich outer surface

Vertical transistor including a bottom source/drain region, a gate structure, and an air gap formed between the bottom source/drain region and the gate structure

Forming wrap-around silicide contact on finFET

Self aligned top extension formation for vertical transistors

Vertical FET with strained channel

Self-aligned inner-spacer replacement process using implantation

Voidless contact metal structures

Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance

Three-dimensional field effect device

Inner spacer formation and contact resistance reduction in nanosheet transistors

Vertical fin field effect transistor devices with self-aligned source and drain junctions

Gate metal patterning to avoid gate stack attack due to excessive wet etching

Method and structure for forming vertical transistors with various gate lengths

Bottom isolation for nanosheet transistors on bulk substrate

Nanosheet device with close source drain proximity

Vertical transport FET (VFET) with dual top spacer

Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy

Localized fin width scaling using a hydrogen anneal

FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation

Self aligned top extension formation for vertical transistors

Vertical transport fin field effect transistors having different channel lengths

Low resistance source drain contact formation

Bottom spacer formation for vertical transistor

Method of forming vertical transistor having dual bottom spacers

Forming a fin using double trench epitaxy

Forming a contact for a semiconductor device

Transistor and method of forming same

Designable channel FinFET fuse

Vertical transistor bottom spacer formation

Semiconductor device structure with 110-PFET and 111-NFET curent flow direction

Dielectric isolated SiGe fin on bulk substrate

Forming a fin using double trench epitaxy

Localized elastic strain relaxed buffer

Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction

Tall relaxed high percentage silicon germanium fins on insulator

Non-merged epitaxially grown MOSFET devices