Inventor

FARRELL MARK S

US136 patents

⚠️ This page may combine multiple inventors who share the name “FARRELL MARK S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FARRELL MARK S

IBM

Memory mapped Input/Output operations

Virtualization of an I/O adapter port using enablement and activation functions

Information handling system with virtualized I/O adapter ports

Use of test protection instruction in computing environments that support pageable guests

Method and apparatus for adjusting a time of day clock without adjusting the stepping rate of an oscillator

Method and apparatus for managing the execution of a broadcast instruction on a guest processor

Logical resource partitioning of a data processing system

Intra-instructional transaction abort handling

Controlling operation of a run-time instrumentation facility from a lesser-privileged state

Use of test protection instruction in computing environments that support pageable guests

Performing a configuration virtual topology change and instruction therefore

Performing a configuration virtual topology change and instruction therefore

Computer configuration virtual topology discovery and instruction therefore

Memory mapped input/output virtualization

Memory mapped input/output emulation

Method and system for managing the result from a translator co-processor in a pipelined processor

Efficiency for coordinated start interpretive execution exit for a multithreaded processor

Execution of an instruction for performing a configuration virtual topology change

Test pending external interruption instruction

Address expansion and contraction in a multithreading computer system

Thread context preservation in a multithreading computer system

Managing storage protection faults

Managing storage protection faults

Dynamic enablement of multithreading

Dispatching multiple threads in a computer

Store peripheral component interconnect (PCI) function controls instruction

Use of test protection instruction in computing environments that support pageable guests

Use of test protection instruction in computing environments that support pageable guests

Executing an instruction for performing a configuration virtual topology change

Apparatus and computer program product for TOD-clock steering

General-purpose processor instruction to perform compression/decompression operations

Specialized millicode instruction for range checking

Sort and merge instruction for a general-purpose processor

Managing storage protection faults

Execution of an instruction for performing a configuration virtual topology change

Execution of an instruction for performing a configuration virtual topology change

Address expansion and contraction in a multithreading computer system

FARRELL MARK S

Managing use of storage by multiple pageable guests of a computing environment

Determining the status of run-time-instrumentation controls

Executing an instruction for performing a configuration virtual topology change

Use of test protection instruction in computing environments that support pageable guests

Modifying run-time-instrumentation controls from a lesser-privileged state

CRADDOCK DAVID

Controlling access by a configuration to an adapter function

Controlling the selectively setting of operational parameters for an adapter

Converting a message signaled interruption into an I/O adapter event notification

Identification of types of sources of adapter interruptions

MEANEY PATRICK J

Method, system and computer program product for processing error information in a system

INTERNAT BUSINESS MACHINESS CORP

Computer configuration virtual topology discovery and instruction therefore

ALEXANDER KHARY J

Facilitating processing in a computing environment using an extended drain instruction

BELMAR BRENTON F

Controlling a rate at which adapter interruption requests are processed