Inventor

BELYANSKY MICHAEL P

US56 patents

⚠️ This page may combine multiple inventors who share the name “BELYANSKY MICHAEL P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BELYANSKY MICHAEL P

IBM

Structure and method to improve channel mobility by gate electrode stress modification

Oxidation method for altering a film structure and CMOS transistor structure formed therewith

Method of protecting semiconductor areas while exposing a gate

Method of producing highly strained PECVD silicon nitride thin films at low temperature

Resist having tuned interface hardmask layer for EUV exposure

Filling high aspect ratio isolation structures with polysilazane based material

Vertical transport FET (VFET) with dual top spacer

Controlling gate profile by inter-layer dielectric (ILD) nanolaminates

Self-aligned punchthrough stop doping in bulk finFET by reflowing doped oxide

Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication same

Method of forming self-aligned low-k gate cap

Self-aligned low-k gate cap

CMOS transistor structure including film having reduced stress by exposure to atomic oxygen

Method of making thermally stable planarizing films

Method of forming gate stack and structure thereof

HDP process for high aspect ratio gap filling

Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating same

Method of fabricating mobility enhanced CMOS devices

Stressed semiconductor device structures having granular semiconductor material

Uniform horizontal spacer

Encapsulation layer for vertical transport field-effect transistor gate stack

Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)

Stress modulation of nFET and pFET fin structures

Uniform bottom spacer for vertical field effect transistor

Self-aligned punchthrough stop doping in bulk finFET by reflowing doped oxide

Reduced dielectric constant spacer materials integration for high speed logic gates

Self-aligned gate cap including an etch-stop layer

Uniform horizontal spacer

Vertical fin field effect transistor devices with a replacement metal gate

Vertical fin field effect transistor devices with a replacement metal gate

Vertical transport field-effect transistor (VFET) with dual top spacer

Vertical fin field effect transistor devices with a replacement metal gate

Stress modulation of nFET and pFET fin structures

Dual oxide stress liner

Structure and method to improve channel mobility by gate electrode stress modification

Oxidation method for altering a film structure

Field effect transistors with dielectric source drain halo regions and reduced miller capacitance

Field effect transistors with dielectric source drain halo regions and reduced miller capacitance

Forming collar structures in deep trench capacitors with thermally stable filler material

Silicon handler with laser-release layers

Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)

Protection of low temperature isolation fill

Infrared debond damage mitigation by copper fill pattern

Self-aligned gate cap including an etch-stop layer

Transistor having straight bottom spacers

Stressed material within gate cut region

Highly selective dry etch process for vertical FET STI recess

Vertical fin field effect transistor devices with a replacement metal gate

VENIGALLA RAJASEKHAR

Method for controlling structure height

ELPIS TECH INC

Controlling gate profile by inter-layer dielectric (ILD) nanolaminates