Inventor

TSUTSUI GEN

US41 patents

⚠️ This page may combine multiple inventors who share the name “TSUTSUI GEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSUTSUI GEN

IBM

Cutting fins and gates in CMOS devices

Enabling low resistance gates and contacts integrated with bilayer dielectrics

FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation

Formation of stacked vertical transport field effect transistors

Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)

Hybrid BEOL metallization utilizing selective reflection mask

FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation

Interface charge reduction for SiGe surface

FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation

Self-aligned doping in source/drain regions for low contact resistance

Bottom contact with self-aligned spacer for stacked semiconductor devices

Bottom source/drain for fin field effect transistors

Bottom source/drain for fin field effect transistors

Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS

Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS

Forming gate all around device with silicon-germanium channel

Single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET

Stacked-FET SRAM cell with bottom pFET

Non-step nanosheet structure for stacked field-effect transistors

Vertical transport field effect transistor with bottom source/drain

Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)

Differing device characteristics on a single wafer by selective etch

Vertical transport field effect transistor with bottom source/drain

Interface charge reduction for SiGe surface

Hybrid BEOL metallization utilizing selective reflection mask

Semiconductor device with mitigated local layout effects

Forming MOSFET structures with work function modification

Unipolar-FET implementation in stacked-FET CMOS

Fin isolation to mitigate local layout effects

Differing device characteristics on a single wafer by selective etch

Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects

Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared pFET and nFET trench

Self-aligned doping in source/drain regions for low contact resistance

Forming MOSFET structures with work function modification

Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared PFET and NFET trench

Semiconductor device including fin having condensed channel region

IWAMOTO TOSHIYUKI

Semiconductor device and method of manufacturing the semiconductor device

Hybrid planarFET and FinFET provided on a chip

BRYANT ANDRES

Reducing gate resistance in nonplanar multi-gate transistor

TSUTSUI GEN

Method of manufacturing semiconductor device, and semiconductor device

RENESAS ELECTRONICS CORP

Semiconductor device and method of manufacturing the semiconductor device