Inventor · disambiguated record
Ajay Sudarshan Tirumala
Also filed as: TIRUMALA AJAY · TIRUMALA AJAY S · TIRUMALA AJAY SUDARSHAN
11 granted patents·3 pending applications·11 citations·filing 2015–2024
82Inventor score
Top patents by PatentIndex Score
14 records- 0187US10977037B2Techniques for comprehensively synchronizing execution threadsNVIDIA CORP·Filed 2019·Granted Apr 13, 2021·5 cites·20 claims
- 0279US10877757B2Binding constants at runtime for improved resource utilizationNVIDIA CORP·Filed 2018·Granted Dec 29, 2020·3 cites·20 claims
- 0378US11550584B1Implementing specialized instructions for accelerating Smith-Waterman sequence alignmentsNVIDIA CORP·Filed 2021·Granted Jan 10, 2023·1 cites·20 claims
- 0473US10067768B2Execution of divergent threads using a convergence barrierNVIDIA CORP·Filed 2015·Granted Sep 4, 2018·2 cites·20 claims
- 0561US12141582B2Implementing specialized instructions for accelerating dynamic programming algorithmsNVIDIA CORP·Filed 2022·Granted Nov 12, 2024·0 cites·20 claims
- 0658US2025021622A1Efficient vector-matrix multiply operations across parallel processing unit threadsNVIDIA CORP·Filed 2024·Application pending·0 cites
- 0758US2023101085A1Techniques for accelerating smith-waterman sequence alignmentsNVIDIA CORP·Filed 2021·Application pending·0 cites
- 0855US10866806B2Uniform register file for improved resource utilizationNVIDIA CORP·Filed 2018·Granted Dec 15, 2020·0 cites·20 claims
- 0954US10437593B2Techniques for comprehensively synchronizing execution threadsNVIDIA CORP·Filed 2017·Granted Oct 8, 2019·0 cites·20 claims
- 1053US11061741B2Techniques for efficiently performing data reductions in parallel processing unitsNVIDIA CORP·Filed 2019·Granted Jul 13, 2021·0 cites·17 claims
- 1150US11822541B2Techniques for storing sub-alignment data when accelerating Smith-Waterman sequence alignmentsNVIDIA CORP·Filed 2021·Granted Nov 21, 2023·0 cites·20 claims
- 1249US12271765B2Techniques for efficiently synchronizing multiple program threadsNVIDIA CORP·Filed 2021·Granted Apr 8, 2025·0 cites·20 claims
- 1349US2025291873A1Universal Scale Metadata Layout for Matrix Multiply and Add (MMA)NVDIA CORP·Filed 2024·Application pending·0 cites
- 1448US10817295B2Thread-level sleep in a multithreaded architectureNVIDIA CORP·Filed 2017·Granted Oct 27, 2020·0 cites·21 claims
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