Inventor

MCDONALD JOSEPH GERALD

US15 patents

⚠️ This page may combine multiple inventors who share the name “MCDONALD JOSEPH GERALD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

9 patents

US6334162B1Dec 25, 2001

Efficient data transfer mechanism for input/out devices having a device driver generating a descriptor queue and monitoring a status queue

IBM51 citations95

US6049842AApr 11, 2000

System for collecting a specified number of peripheral interrupts and transferring the interrupts as a group to the processor

IBM55 citations92

US6073181AJun 6, 2000

Multi-buffer error detection for an open data-link interface LAN adapter

IBM24 citations91

US6185207B1Feb 6, 2001

Communication system having a local area network adapter for selectively deleting information and method therefor

IBM26 citations89

US6338102B1Jan 8, 2002

Efficient data transfer mechanism for input/output devices having a device driver generating a descriptor queue and monitoring a status queue

IBM12 citations81

QUALCOMM INC

4 patents

US11550723B2Jan 10, 2023

Method, apparatus, and system for memory bandwidth aware data prefetching

QUALCOMM INC2 citations70

US11226910B2Jan 18, 2022

Ticket based request flow control

QUALCOMM INC0 citations60

US11016899B2May 25, 2021

Selectively honoring speculative memory prefetch requests based on bandwidth state of a memory access path component(s) in a processor-based system

QUALCOMM INC0 citations48

US9594713B2Mar 14, 2017

Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media

QUALCOMM INC0 citations47

BASS BRIAN MITCHELL

1 patent

US9448846B2Sep 20, 2016

Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines

BASS BRIAN MITCHELL3 citations70

DALY JR GEORGE WILLIAM

1 patent

US8230117B2Jul 24, 2012

Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline

DALY JR GEORGE WILLIAM0 citations45

MCDONALD JOSEPH GERALD

IBM

Efficient data transfer mechanism for input/out devices having a device driver generating a descriptor queue and monitoring a status queue

Efficient data transfer mechanism for input/output devices

Queue management for networks employing pause time based flow control

Efficient data transfer mechanism for input/output devices

Efficient data transfer mechanism for input/output devices

System for collecting a specified number of peripheral interrupts and transferring the interrupts as a group to the processor

Multi-buffer error detection for an open data-link interface LAN adapter

Communication system having a local area network adapter for selectively deleting information and method therefor

Efficient data transfer mechanism for input/output devices having a device driver generating a descriptor queue and monitoring a status queue

QUALCOMM INC

Method, apparatus, and system for memory bandwidth aware data prefetching

Ticket based request flow control

Selectively honoring speculative memory prefetch requests based on bandwidth state of a memory access path component(s) in a processor-based system

Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media

BASS BRIAN MITCHELL

Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines

DALY JR GEORGE WILLIAM

Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline