Inventor

PARK TAI-SU

KR37 patents

⚠️ This page may combine multiple inventors who share the name “PARK TAI-SU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARK TAI-SU

SAMSUNG ELECTRONICS CO LTD

Method for forming a trench isolation structure in an integrated circuit

Methods for forming isolation trenches including doped silicon oxide

Vertical channel field effect transistors having insulating layers thereon

Trench isolation structure, semiconductor device having the same, and trench isolation method

Methods of forming semiconductor device

Trench isolation regions having recess-inhibiting layers therein that protect against overetching

Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching

Semiconductor device having a Y-shaped isolation layer and simplified method for manufacturing the Y-shaped isolation layer to prevent divot formation

Semiconductor device having a trench isolation structure

Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step

Method of forming shallow trench isolation layer in semiconductor device

Trench isolation regions having trench liners with recessed ends

Method for forming a trench isolation in a semiconductor device

Silicon nitride-free isolation methods for integrated circuits

Annealing methods for forming isolation trenches

Methods of forming combined trench and locos-based electrical isolation regions in semiconductor substrates

Device isolation method in integrated circuits

Double gate field effect transistor and method of manufacturing the same

Fin field effect transistor and method of fabricating the same

Methods of manufacturing trench isolation structures using selective plasma ion immersion implantation and deposition (PIIID)

Methods of fabricating semiconductor device having shallow trench isolation (STI)

Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step

Method of forming isolation film for semiconductor devices

Manufacturing method for filling a trench or contact hole in a semiconductor device

Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing

Double gate field effect transistor and method of manufacturing the same

Semiconductor device having a trench isolation structure and method for fabricating the same

Methods of manufacturing semiconductor devices

Methods of fabricating vertical channel field effect transistors having insulating layers thereon

Method of fabricating semiconductor device

Opening filling apparatus for manufacturing a semiconductor device

PARK TAI-SU

Semiconductor devices having nitrided gate insulating layer and methods of fabricating the same

Methods of forming recessed channel array transistors and methods of manufacturing semiconductor devices

Methods of fabricating gate insulating layers in gate trenches and methods of fabricating semiconductor devices including the same

RYU JEONG-DO

Recessed channel array transistors, and semiconductor devices including a recessed channel array transistor

Methods of forming integrated circuit devices having electrically conductive layers therein with partially nitridated sidewalls

Methods of forming integrated circuit devices having electrically conductive layers therein with partially nitridated sidewalls