Inventor
KUANG JENTE BENEDICT
US25 patents
⚠️ This page may combine multiple inventors who share the name “KUANG JENTE BENEDICT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
21 patentsUS6504212B1Jan 7, 2003
Method and apparatus for enhanced SOI passgate operations
IBM85 citations97
US6281737B1Aug 28, 2001
Method and apparatus for reducing parasitic bipolar current in a silicon-on-insulator transistor
IBM101 citations96
US6222394B1Apr 24, 2001
SOI CMOS sense amplifier with enhanced matching characteristics and sense point tolerance
IBM57 citations96
US7219244B2May 15, 2007
Control circuitry for power gating virtual power supply rails at differing voltage potentials
IBM27 citations92
US6608785B2Aug 19, 2003
Method and apparatus to ensure functionality and timing robustness in SOI circuits
IBM44 citations92
US6448830B1Sep 10, 2002
Single-stage tri-state Schmitt trigger
IBM35 citations92
US6441663B1Aug 27, 2002
SOI CMOS Schmitt trigger circuits with controllable hysteresis
IBM42 citations92
US6373281B1Apr 16, 2002
Tri-state dynamic body charge modulation for sensing devices in SOI RAM applications
IBM18 citations92
US7952422B2May 31, 2011
Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices
IBM11 citations84
US7336105B2Feb 26, 2008
Dual gate transistor keeper dynamic logic
IBM9 citations84
US6635518B2Oct 21, 2003
SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies
IBM15 citations84
US7202705B2Apr 10, 2007
Dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control
IBM11 citations82
US6404686B1Jun 11, 2002
High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus
IBM9 citations73
US6252429B1Jun 26, 2001
Method and apparatus for improving device matching and switching point tolerance in silicon-on-insulator cross-coupled circuits
IBM11 citations73
US7692480B2Apr 6, 2010
System to evaluate a voltage in a charge pump and associated methods
IBM7 citations71
US7265589B2Sep 4, 2007
Independent gate control logic circuitry
IBM2 citations63
US7142015B2Nov 28, 2006
Fast turn-off circuit for controlling leakage
IBM6 citations63
US7193446B2Mar 20, 2007
Dynamic logic circuit incorporating reduced leakage state-retaining devices
IBM4 citations61
US6392855B1May 21, 2002
Floating body charge monitor circuit for partially depleted SOI CMOS technology
IBM4 citations61
US7876131B2Jan 25, 2011
Dual gate transistor keeper dynamic logic
IBM0 citations52
US7216141B2May 8, 2007
Computing carry-in bit to most significant bit carry save adder in current stage
IBM0 citations51