Inventor
WIJERATNE SAPUMAL
US13 patents
Patents
13 patentsUS7509368B2Mar 24, 2009
Sparse tree adder circuit
INTEL CORP32 citations89
US7656702B2Feb 2, 2010
Ultra low voltage, low leakage, high density, variation tolerant memory bit cells
INTEL CORP9 citations76
US7016239B2Mar 21, 2006
Leakage tolerant register file
INTEL CORP9 citations71
US7002855B2Feb 21, 2006
Leakage tolerant register file
INTEL CORP7 citations66
US7325024B2Jan 29, 2008
Adder circuit with sense-amplifier multiplexer front-end
INTEL CORP6 citations62
US7202703B2Apr 10, 2007
Single stage level restore circuit with hold functionality
INTEL CORP3 citations61
US6958629B2Oct 25, 2005
Single stage, level restore circuit with mixed signal inputs
INTEL CORP2 citations61
US6922082B2Jul 26, 2005
Select logic for low voltage swing circuits
INTEL CORP3 citations61
US7161389B2Jan 9, 2007
Ratioed logic circuits with contention interrupt
INTEL CORP3 citations60
US11275663B2Mar 15, 2022
Fast dynamic capacitance, frequency, and/or voltage throttling apparatus and method
INTEL CORP0 citations58
US12235792B2Feb 25, 2025
Apparatus and method for temperature-constrained frequency control and scheduling
INTEL CORP0 citations55
US7516173B2Apr 7, 2009
Carry-skip adder having merged carry-skip cells with sum cells
INTEL CORP1 citations51
US6836755B2Dec 28, 2004
Method and apparatus for fully automated signal integrity analysis for domino circuitry
INTEL CORP0 citations39