Inventor

WAIDHAS BERND

DE61 patents

⚠️ This page may combine multiple inventors who share the name “WAIDHAS BERND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WAIDHAS BERND

INTEL CORP

Wearable electronic devices and components thereof

Wearable electronic devices and components thereof

Chip scale thin 3D die stacked package

Bare-die smart bridge connected with copper pillars for system-in-package apparatus

Printed wiring-board islands for connecting chip packages and methods of assembling same

Fan out packaging pop mechanical attach method

Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory

Method to implement wafer-level chip-scale packages with grounded conformal shield

Assembly of 2XD module using high density interconnect bridges

Bare-die smart bridge connected with copper pillars for system-in-package apparatus

Assembly of 2XD module using high density interconnect bridges

Vertical and lateral interconnects between dies

Fan out package with integrated peripheral devices and methods

Fan out packaging pop mechanical attach method

Microelectronic assemblies having topside power delivery structures

Antenna with graded dielectirc and method of making the same

Package formation methods including coupling a molded routing layer to an integrated routing layer

Fan out package with integrated peripheral devices and methods

Printed wiring-board islands for connecting chip packages and methods of assembling same

Fan out package and methods

Systems, methods, and apparatuses for implementing reduced height semiconductor packages for mobile electronics

Magnetic coils in locally thinned silicon bridges and methods of assembling same

Face-up fan-out electronic package with passive components using a support

Semiconductor inductors

Stress relief die implementation

Method to implement wafer-level chip-scale packages with grounded conformal shield

Bare-die smart bridge connected with copper pillars for system-in-package apparatus

Semiconductor packages, and methods for forming semiconductor packages

INTEL IP CORP

Antenna with graded dielectirc and method of making the same

Package including an integrated routing layer and a molded routing layer

Face-up fan-out electronic package with passive components using a support

Component magnetic shielding for microelectronic devices

Semiconductor package having a variable redistribution layer thickness

Semiconductor package having a variable redistribution layer thickness

Fan out package with integrated peripheral devices and methods

Fan out package-on-package with adhesive die attach

Lead frame with angular deflections and wrapped printed wiring boards for system-in-package apparatus

Power mesh-on-die trace bumping

Molded substrate package in fan-out wafer level package

Interconnect structure for a microelectronic device

Power mesh-on-die trace bumping

Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory

Carrier substrate for a semiconductor device and a method for forming a carrier substrate for a semiconductor device

INFINEON TECHNOLOGIES AG

Electronic package having integrated cooling element with clearance for engaging package

Optoelectronic surface-mountable module and optoelectronic coupling unit

Electronic component and electronic configuration

MEYER THORSTEN

Enhanced flip chip package

Semiconductor component including a semiconductor chip and a passive component

INTEL DEUTSCHLAND GMBH

Semiconductor devices

INTEL MOBILE COMM GMBH

Enhanced flip chip package