P

Inventor

FLEISCHER BRUCE

US17 patents

Patents

17 patents
US10656913B2May 19, 2020

Enhanced low precision binary floating-point formatting

IBM9 citations84
US11138010B1Oct 5, 2021

Loop management in multi-processor dataflow architecture

IBM7 citations83
US11157280B2Oct 26, 2021

Dynamic fusion based on operand size

IBM4 citations72
US11669489B2Jun 6, 2023

Sparse systolic array design

IBM2 citations71
US11620132B2Apr 4, 2023

Reusing an operand received from a first-in-first-out (FIFO) buffer according to an operand specifier value specified in a predefined field of an instruction

IBM2 citations71
US11095313B2Aug 17, 2021

Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures

IBM2 citations66
US11775257B2Oct 3, 2023

Enhanced low precision binary floating-point formatting

IBM0 citations62
US11182127B2Nov 23, 2021

Binary floating-point multiply and scale operation for compute-intensive numerical applications and apparatuses

IBM0 citations62
US11347517B2May 31, 2022

Reduced precision based programmable and SIMD dataflow architecture

IBM0 citations61
US10838868B2Nov 17, 2020

Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory components

IBM1 citations60
US11860702B2Jan 2, 2024

Current consumption controller

IBM0 citations52
US11314482B2Apr 26, 2022

Low latency floating-point division operations

IBM0 citations51
US11281745B2Mar 22, 2022

Half-precision floating-point arrays at low overhead

IBM0 citations51
US11223703B2Jan 11, 2022

Instruction initialization in a dataflow architecture

IBM0 citations51
US10565285B2Feb 18, 2020

Processor and memory transparent convolutional lowering and auto zero padding for deep neural network implementations

IBM0 citations51
US11455142B2Sep 27, 2022

Ultra-low precision floating-point fused multiply-accumulate unit

IBM0 citations50
US11216281B2Jan 4, 2022

Facilitating data processing using SIMD reduction operations across SIMD lanes

IBM0 citations49