Inventor
RANJAN NALINI
US9 patents
Patents
9 patentsUS6005412ADec 21, 1999
AGP/DDR interfaces for full swing and reduced swing (SSTL) signals on an integrated circuit chip
S3 INC62 citations95
US5862390AJan 19, 1999
Mixed voltage, multi-rail, high drive, low noise, adjustable slew rate input/output buffer
S3 INC69 citations95
US6040737AMar 21, 2000
Output buffer circuit and method that compensate for operating conditions and manufacturing processes
S3 INC43 citations92
US6005432ADec 21, 1999
Voltage level shift system and method
S3 INC24 citations92
US6208167B1Mar 27, 2001
Voltage tolerant buffer
S3 INC33 citations91
US6265899B1Jul 24, 2001
Single rail domino logic for four-phase clocking scheme
S3 INC42 citations86
US5852568ADec 22, 1998
System and method for a fast carry/sum select adder
S3 INC11 citations72
US6393600B1May 21, 2002
Skew-independent memory architecture
S3 INC13 citations71
US6031258AFeb 29, 2000
High DC current stagger power/ground pad
S3 INC15 citations69