Inventor
FROEHLICH HANS-GEORG
DE6 patents
Patents
6 patentsUS7425396B2Sep 16, 2008
Method for reducing an overlay error and measurement mark for carrying out the same
INFINEON TECHNOLOGIES AG19 citations79
US7018781B2Mar 28, 2006
Method for fabricating a contact hole plane in a memory module
INFINEON TECHNOLOGIES AG9 citations69
US7084962B2Aug 1, 2006
Method for detecting positioning errors of circuit patterns during the transfer by means of a mask into layers of a substrate of a semiconductor wafer
INFINEON TECHNOLOGIES AG7 citations68
US7251016B2Jul 31, 2007
Method for correcting structure-size-dependent positioning errors in photolithography
INFINEON TECHNOLOGIES AG2 citations56
US6750554B2Jun 15, 2004
Mark configuration, wafer with at least one mark configuration and method for the fabrication of at least one mark configuration
INFINEON TECHNOLOGIES AG0 citations50
US6982495B2Jan 3, 2006
Mark configuration, wafer with at least one mark configuration, and a method of producing at least one mark configuration
INFINEON TECHNOLOGIES AG0 citations41