Inventor

DERVISOGLU BULENT I

US7 patents

⚠️ This page may combine multiple inventors who share the name “DERVISOGLU BULENT I”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HEWLETT PACKARD CO

2 patents

US5257223AOct 26, 1993

Flip-flop circuit with controllable copying between slave and scan latches

HEWLETT PACKARD CO138 citations96

US5068881ANov 26, 1991

Scannable register with delay test capability

HEWLETT PACKARD CO28 citations91

DERVISOGLU BULENT I

2 patents

US7752515B2Jul 6, 2010

Accelerated scan circuitry and method for reducing scan test data volume and execution time

DERVISOGLU BULENT I10 citations82

US8239716B2Aug 7, 2012

On-chip service processor

DERVISOGLU BULENT I4 citations71

INTELLITECH CORP

1 patent

US6594802B1Jul 15, 2003

Method and apparatus for providing optimized access to circuits for debug, programming, and test

INTELLITECH CORP143 citations96

INTELLECTUAL VENTURES I LLC

1 patent

US7890899B2Feb 15, 2011

Variable clocked scan test improvements

INTELLECTUAL VENTURES I LLC27 citations92

ON CHIP TECHNOLOGIES INC

1 patent

US7353470B2Apr 1, 2008

Variable clocked scan test improvements

ON CHIP TECHNOLOGIES INC27 citations92