Inventor

CODINA ENRIC GIBERT

ES9 patents

⚠️ This page may combine multiple inventors who share the name “CODINA ENRIC GIBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

4 patents

US10621092B2Apr 14, 2020

Merging level cache and data cache units having indicator bits related to speculative execution

INTEL CORP1 citations60

US9389871B2Jul 12, 2016

Combined floating point multiplier adder with intermediate rounding logic

INTEL CORP0 citations51

US9983880B2May 29, 2018

Method and apparatus for improved thread selection

INTEL CORP1 citations46

US10157063B2Dec 18, 2018

Instruction and logic for optimization level aware branch prediction

INTEL CORP0 citations36

LATORRE FERNANDO

1 patent

US8909902B2Dec 9, 2014

Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution

LATORRE FERNANDO10 citations80

LOPEZ PEDRO

1 patent

US9940138B2Apr 10, 2018

Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculations

LOPEZ PEDRO5 citations71

LUPON MARC

1 patent

US9329848B2May 3, 2016

Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs

LUPON MARC4 citations66

MARTINEZ RAUL

1 patent

US9116719B2Aug 25, 2015

Partial commits in dynamic binary translation based systems

MARTINEZ RAUL1 citations50

CODINA ENRIC GIBERT

1 patent

US8898646B2Nov 25, 2014

Method and apparatus for flexible, accurate, and/or efficient code profiling

CODINA ENRIC GIBERT1 citations44