Inventor · disambiguated record
William R. Halleck
Also filed as: HALLECK WILLIAM · HALLECK WILLIAM R
20 granted patents·3 pending applications·157 citations·filing 2005–2023
94Inventor score
Top patents by PatentIndex Score
23 records- 0195US7376789B2Wide-port context cache apparatus, systems, and methodsINTEL CORP·Filed 2005·Granted May 20, 2008·48 cites·26 claims
- 0294US10795853B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2017·Granted Oct 6, 2020·9 cites·24 claims
- 0392US10152446B2Link-physical layer interface adapterINTEL CORP·Filed 2016·Granted Dec 11, 2018·10 cites·11 claims
- 0491US11586579B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2021·Granted Feb 21, 2023·2 cites·24 claims
- 0591US7415549B2DMA completion processing mechanismINTEL CORP·Filed 2005·Granted Aug 19, 2008·44 cites·18 claims
- 0687US10599602B2Bimodal phy for low latency in high speed interconnectsINTEL CORP·Filed 2019·Granted Mar 24, 2020·3 cites·23 claims
- 0782US10931329B2High speed interconnect with channel extensionINTEL CORP·Filed 2016·Granted Feb 23, 2021·4 cites·11 claims
- 0880US10963415B2Bimodal PHY for low latency in high speed interconnectsINTEL CORP·Filed 2020·Granted Mar 30, 2021·1 cites·21 claims
- 0980US7797463B2Hardware assisted receive channel frame handling via data offset comparison in SAS SSP wide port applicationsINTEL CORP·Filed 2005·Granted Sep 14, 2010·9 cites·19 claims
- 1078US7664889B2DMA descriptor management mechanismINTEL CORP·Filed 2005·Granted Feb 16, 2010·11 cites·10 claims
- 1176US11899615B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2023·Granted Feb 13, 2024·0 cites·24 claims
- 1274US10372657B2Bimodal PHY for low latency in high speed interconnectsINTEL CORP·Filed 2016·Granted Aug 6, 2019·1 cites·30 claims
- 1372US9910809B2High performance interconnect link state transitionsINTEL CORP·Filed 2014·Granted Mar 6, 2018·2 cites·24 claims
- 1470US11354264B2Bimodal PHY for low latency in high speed interconnectsINTEL CORP·Filed 2021·Granted Jun 7, 2022·0 cites·32 claims
- 1568US7506080B2Parallel processing of frame based data transfersINTER CORP·Filed 2005·Granted Mar 17, 2009·6 cites·16 claims
- 1665US11294852B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2020·Granted Apr 5, 2022·0 cites·25 claims
- 1764US7676604B2Task context direct indexing in a protocol engineINTEL CORP·Filed 2005·Granted Mar 9, 2010·3 cites·13 claims
- 1862US8135869B2Task scheduling to devices with same connection addressCHANG NAICHIH·Filed 2005·Granted Mar 13, 2012·4 cites·11 claims
- 1953US10025746B2High performance interconnectINTEL CORP·Filed 2014·Granted Jul 17, 2018·0 cites·14 claims
- 2050US10324882B2High performance interconnect link state transitionsINTEL CORP·Filed 2016·Granted Jun 18, 2019·0 cites·24 claims
- 2142US2007005898A1Method, apparatus and system for task context cache replacementHALLECK WILLIAM·Filed 2005·Application pending·0 cites
- 2232US2007002827A1Automated serial protocol target port transport layer retry mechanismLAU VICTOR·Filed 2005·Application pending·0 cites
- 2332US2007011333A1Automated serial protocol initiator port transport layer retry mechanismLAU VICTOR·Filed 2005·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →