Inventor
HOULIHAN KEVIN M
US7 patents
Patents
7 patentsUS6504207B1Jan 7, 2003
Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same
IBM67 citations95
US6258673B1Jul 10, 2001
Multiple thickness of gate oxide
IBM69 citations95
US6326275B1Dec 4, 2001
DRAM cell with vertical CMOS transistor
IBM47 citations91
US6893948B2May 17, 2005
Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size
IBM8 citations73
US6670263B2Dec 30, 2003
Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size
IBM9 citations73
US6342431B2Jan 29, 2002
Method for eliminating transfer gate sacrificial oxide
IBM5 citations62
US7714366B2May 11, 2010
CMOS transistor with a polysilicon gate electrode having varying grain size
IBM0 citations51