Inventor
SEE YEE-CHAUNG
US15 patents
⚠️ This page may combine multiple inventors who share the name “SEE YEE-CHAUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MOTOROLA INC
10 patentsUS5892709AApr 6, 1999
Single level gate nonvolatile memory device and method for accessing the same
MOTOROLA INC54 citations96
US5777361AJul 7, 1998
Single gate nonvolatile memory cell and method for accessing the same
MOTOROLA INC67 citations96
US5279978AJan 18, 1994
Process for making BiCMOS device having an SOI substrate
MOTOROLA INC81 citations95
US5212397AMay 18, 1993
BiCMOS device having an SOI substrate and process for making the same
MOTOROLA INC81 citations95
US4775642AOct 4, 1988
Modified source/drain implants in a double-poly non-volatile memory process
MOTOROLA INC60 citations95
US5604700AFeb 18, 1997
Non-volatile memory cell having a single polysilicon gate
MOTOROLA INC34 citations92
US5674762AOct 7, 1997
Method of fabricating an EPROM with high voltage transistors
MOTOROLA INC38 citations91
US5112772AMay 12, 1992
Method of fabricating a trench structure
MOTOROLA INC38 citations89
US5929478AJul 27, 1999
Single level gate nonvolatile memory device and method for accessing the same
MOTOROLA INC46 citations86
US5358883AOct 25, 1994
Lateral bipolar transistor
MOTOROLA INC13 citations73
TEXAS INSTRUMENTS INC
3 patentsUS4374700AFeb 22, 1983
Method of manufacturing silicide contacts for CMOS devices
TEXAS INSTRUMENTS INC173 citations98
US4476482AOct 9, 1984
Silicide contacts for CMOS devices
TEXAS INSTRUMENTS INC40 citations92
US4418094ANov 29, 1983
Vertical-etch direct moat isolation process
TEXAS INSTRUMENTS INC18 citations72