Inventor

HOUSTON THEODORE W

US238 patents

⚠️ This page may combine multiple inventors who share the name “HOUSTON THEODORE W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOUSTON THEODORE W

TEXAS INSTRUMENTS INC

Integrated circuit cells

Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device

SOI DRAM having P-doped poly gate for a memory pass transistor

SOI DRAM having P-doped polysilicon gate for a memory pass transistor

Memory with storage cells having SOI drive and access transistors with tied floating body connections

Memory with storage cells having SOI drive and access transistors with tied floating body connections

Selective power to memory

SRAM device and a method of operating the same to reduce leakage current during a sleep mode

SRAM cell with column select line

SRAM device and a method of powering-down the same

Memory circuits, systems, and methods with cells using back bias to control the threshold voltage of one or more corresponding cell transistors

Method of fabricating a soi transistor with pocket implant and body-to-source (bts) contact

Staggered memory cell array

Comprehensive logic circuit layout system

Bit line control for low power in standby

Double pattern and etch of poly with hard mask

Memory array and wordline driver supply voltage differential in standby

Dynamic threshold voltage 6T SRAM cell

SPIMOX/SIMOX combination with ITOX option

System and method for reducing power dissipation in a circuit

Self-aligned trenched-channel lateral-current-flow transistor

Increased effective transistor width using double sidewall spacers

Buried oxide with a thermal expansion matching layer for SOI

Differential SOI amplifiers having tied floating body connections

Optimizing the operating characteristics of a CMOS integrated circuit

Single event upset hardened memory cell

Pulse generator circuit and method

Method and system for screening reliability of semiconductor circuits

Method of making extended body contact for semiconductor over insulator transistor

Memory with selective address transition detection for cache operation

Multiple compound domino logic circuit

Memory having selected state on power-up

Area efficient implementation of small blocks in an SRAM array

Semiconductor on silicon (SOI) transistor with a halo implant

Reducing non-uniformity in a refill layer thickness for a semiconductor device

Integrated DRAM process/structure using contact pillars

SRAM cell using separate read and write circuitry

SRAM bias for read and write

SRAM cell using separate read and write circuitry

Memory array with a delayed wordline boost

Low leakage SRAM scheme

Integrated circuit cells

Column voltage control for write

Method and apparatus for reducing leakage current in an SRAM array

Integrated circuit cells

Loadless 4T SRAM cell with PMOS drivers

Integrated DRAM process/structure using contact pillars

Static random access memory cell and method

SRAM with write-back on read

SUN MICROSYSTEMS INC

Tunable threshold SOI device using back gate well