Inventor
KANTER OFIR
IL21 patents
⚠️ This page may combine multiple inventors who share the name “KANTER OFIR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
KIOXIA CORP
17 patentsUS12050514B1Jul 30, 2024
Deep neural network implementation for soft decoding of BCH code
KIOXIA CORP10 citations85
US11563450B1Jan 24, 2023
System and method for high reliability fast RAID decoding for NAND flash memories
KIOXIA CORP7 citations85
US11258466B1Feb 22, 2022
System and method for high reliability fast raid soft decoding for NAND flash memories
KIOXIA CORP8 citations85
US11689219B1Jun 27, 2023
Method and system for error correction in memory devices using irregular error correction code components
KIOXIA CORP4 citations74
US12283972B2Apr 22, 2025
Method and system for error correction in memory devices using irregular error correction code components
KIOXIA CORP0 citations62
US12260129B2Mar 25, 2025
Tracking and updating read command voltage thresholds in solid-state drives
KIOXIA CORP0 citations62
US12197283B2Jan 14, 2025
Efficient hard decoding of error correction code via extrinsic bit information
KIOXIA CORP0 citations62
US12189476B2Jan 7, 2025
Soft error detection and correction for data storage devices
KIOXIA CORP0 citations62
US12119075B2Oct 15, 2024
Efficient soft decoding of error correction code via extrinsic bit information
KIOXIA CORP0 citations62
US11693733B2Jul 4, 2023
Soft error detection and correction for data storage devices
KIOXIA CORP0 citations62
US12210412B2Jan 28, 2025
Hard decoding methods in data storage devices
KIOXIA CORP0 citations59
US12176924B2Dec 24, 2024
Deep neural network implementation for concatenated codes
KIOXIA CORP0 citations59
US11513894B2Nov 29, 2022
Hard decoding methods in data storage devices
KIOXIA CORP0 citations59
US11790984B1Oct 17, 2023
Clustering for read thresholds history table compression in NAND storage systems
KIOXIA CORP0 citations53
US12009840B2Jun 11, 2024
Systems and methods of decoding error correction code of a memory device with dynamic bit error estimation
KIOXIA CORP0 citations52
US11734107B2Aug 22, 2023
Decoding scheme for error correction code structure
KIOXIA CORP0 citations48
US12095481B2Sep 17, 2024
Efficient decoding schemes for error correcting codes for memory devices
KIOXIA CORP0 citations47
INTEL CORP
3 patentsUS7516380B2Apr 7, 2009
BIST to provide jitter data and associated methods of operation
INTEL CORP5 citations60
US7539916B2May 26, 2009
BIST to provide phase interpolator data and associated methods of operation
INTEL CORP4 citations55
US7552366B2Jun 23, 2009
Jitter tolerance testing apparatus, systems, and methods
INTEL CORP0 citations50