Inventor
PAWASHE CHYTRA
US13 patents
⚠️ This page may combine multiple inventors who share the name “PAWASHE CHYTRA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
12 patentsUS10242892B2Mar 26, 2019
Micro pick and bond assembly
INTEL CORP5 citations82
US11056356B1Jul 6, 2021
Fluid viscosity control during wafer bonding
INTEL CORP5 citations70
US10720345B1Jul 21, 2020
Wafer to wafer bonding with low wafer distortion
INTEL CORP3 citations69
US11721554B2Aug 8, 2023
Stress compensation for wafer to wafer bonding
INTEL CORP2 citations68
US11171057B2Nov 9, 2021
Semiconductor fin design to mitigate fin collapse
INTEL CORP0 citations62
US11195719B2Dec 7, 2021
Reducing in-plane distortion from wafer to wafer bonding using a dummy wafer
INTEL CORP0 citations60
US10886153B2Jan 5, 2021
Display including an LED element having a pressure sensitive adhesive (PSA) for micro pick and bond assembly of the display
INTEL CORP1 citations60
US9947805B2Apr 17, 2018
Nanowire-based mechanical switching device
INTEL CORP0 citations51
US10457548B2Oct 29, 2019
Integrating MEMS structures with interconnects and vias
INTEL CORP0 citations50
US10282965B2May 7, 2019
Synthetic jet delivering controlled flow to sensor system
INTEL CORP0 citations50
US9926193B2Mar 27, 2018
Magnetic nanomechanical devices for stiction compensation
INTEL CORP0 citations49
US10707186B1Jul 7, 2020
Compliant layer for wafer to wafer bonding
INTEL CORP0 citations40