Inventor

LEE RUBY B

US41 patents

⚠️ This page may combine multiple inventors who share the name “LEE RUBY B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE RUBY B

HEWLETT PACKARD CO

Processor for performing subword permutations and combinations

Performance of an operation on whole word operands and on operations in parallel on sub-word operands in a single processor

Parallel shift and add circuit and method

Efficient hardware handling of positive and negative overflow resulting from arithmetic operations

Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward software compatibility

Bidirectional branch prediction and optimization

Method and apparatus for facilitating instruction processing of a digital computer

Cache memory with variable fetch and replacement schemes

Method and apparatus for fast digital signal decoding

Apparatus and method for nullifying delayed slot instructions in a pipelined computer system

Shift and rounding circuit and method

Maximal length immediates with fixed sign position

Software method for implementing dismissible instructions on a computer

Integer multiply instructions incorporating a subresult selection option

TELEPUTERS LLC

Method and system for performing permutations using permutation instructions based on modified omega and flip stages

Method and system for performing permutations with bit permutation instructions

Method and system for performing subword permutation instructions for use in two-dimensional multimedia processing

Method and system for performing permutations using permutation instructions based on butterfly networks

System and method for processor-based security

System and method for processor-based security

System and method for self-protecting data

Method and system for performing permutations with bit permutation instructions

System and method for security health monitoring and attestation of virtual machines in cloud computing systems

Parallel read functional unit for microprocessors

Cache memory having enhanced performance and security features

System and method for self-protecting data

Cache memory having enhanced performance and security features

LEE RUBY B

Hardware trust anchors in SP-enabled processors

System and method for processor-based security

Cache memory having enhanced performance and security features

Microprocessor shifter circuits utilizing butterfly and inverse butterfly routing circuits, and control circuits therefor

HEWLETT PACKARD DEVELOPMENT CO

Image matching using pixel-depth reduction before image comparison

Variable reordering (Mux) instructions for parallel table lookups from registers

Parallel subword instructions for directing results to selected subword locations of data processor result register

Motion estimation using bit-wise block comparisons for video compresssion

CORESECURE TECH LLC

Systems and methods for random fill caching and prefetching for secure cache memories

Systems and methods for random fill caching and prefetching for secure cache memories

System and method for security health monitoring and attestation of virtual machines in cloud computing systems

(unassigned)

Computer multiply instruction with a subresult selection option

UNIV PRINCETON

Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor

STANFORD RES INST INT

Anomalous behavior detection in processor based systems