Inventor

BRUCKERT WILLIAM F

US29 patents

⚠️ This page may combine multiple inventors who share the name “BRUCKERT WILLIAM F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRUCKERT WILLIAM F

DIGITAL EQUIPMENT CORP

Fault tolerant, synchronized twin computer system with error checking of I/O communication

Dual rail processors with error checking on I/O reads

Dual zone, fault tolerant computer system with error checking in I/O writes

Method of handling errors in software

Method of handling errors in software

Dual-rail processor with error checking at single rail interfaces

Pipeline error correction

Interface of non-fault tolerant components to fault tolerant system

Fault tolerant computer systems with fault isolation and repair

Instruction prefetch system for conditional branch instruction for central processor unit

Adjustable buffer for data communications in a data processing system

Buffer system for input/output portion of digital data processing system

Memory for a digital data processing system including circuit for controlling refresh operations during power-up and power-down conditions

HEWLETT PACKARD DEVELOPMENT CO

System and method for configuring adaptive sets of links between routers in a system area network (SAN)

Method and system executing user programs on non-deterministic processors

Method and system of bringing processors to the same computational point

Tuning core voltages of processors

Method and system of determining the execution point of programs executed in lock step

Method and system of executing duplicate copies of a program in lock step

Method and system of copying a memory area between processor elements for lock-step execution

Method and system of copying memory from a source processor to a target processor by duplicating memory writes

Method and system of determining whether a user program has made a system level call

TANDEM COMPUTERS INC

Fail-fast, fail-functional, fault-tolerant multiprocessor system

Clock circuits for synchronized processor systems having clock generator circuit with a voltage control oscillator producing a clock signal synchronous with a master clock signal

Method for verifying responses to messages using a barrier message

COMPAQ COMPUTER CORP

Self-checked, lock step processor pairs

Error self-checking and recovery using lock-step processor pair architecture

BRUCKERT WILLIAM F

Method and system of exchanging information between processors

KLECKA JAMES S

Method and system for presenting an interrupt request to processors executing in lock step