Inventor

SHEPARD JOSEPH F

US40 patents

Patents

40 patents

US5516721AMay 14, 1996

Method of fabricating a semiconductor device with raised diffusions and isolation

IBM79 citations96

US5260233ANov 9, 1993

Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding

IBM51 citations96

US4707218ANov 17, 1987

Lithographic image size reduction

IBM220 citations96

US5622881AApr 22, 1997

Packing density for flash memories

IBM42 citations95

US5245206ASep 14, 1993

Capacitors with roughened single crystal plates

IBM47 citations95

US5384152AJan 24, 1995

Method for forming capacitors with roughened single crystal plates

IBM61 citations94

US4354309AOct 19, 1982

Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon

IBM63 citations94

US5395786AMar 7, 1995

Method of making a DRAM cell with trench capacitor

IBM102 citations93

US5241203AAug 31, 1993

Inverse T-gate FET transistor with lightly doped source and drain region

IBM53 citations93

US5120668AJun 9, 1992

Method of forming an inverse T-gate FET transistor

IBM46 citations93

US4871630AOct 3, 1989

Mask using lithographic image size reduction

IBM68 citations93

US4641170AFeb 3, 1987

Self-aligned lateral bipolar transistors

IBM32 citations93

US4636834AJan 13, 1987

Submicron FET structure and method of making

IBM28 citations93

US4554728ANov 26, 1985

Simplified planarization process for polysilicon filled trenches

IBM27 citations93

US4546535AOct 15, 1985

Method of making submicron FET structure

IBM27 citations93

US5729043AMar 17, 1998

Shallow trench isolation with self aligned PSG layer

IBM24 citations92

US5573964ANov 12, 1996

Method of making thin film transistor with a self-aligned bottom gate using diffusion from a dopant source layer

IBM33 citations92

US5389559AFeb 14, 1995

Method of forming integrated interconnect for very high density DRAMs

IBM46 citations92

US5384277AJan 24, 1995

Method for forming a DRAM trench cell capacitor having a strap connection

IBM36 citations92

US5382832AJan 17, 1995

Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding

IBM21 citations92

US5369049ANov 29, 1994

DRAM cell having raised source, drain and isolation

IBM45 citations92

US5318663AJun 7, 1994

Method for thinning SOI films having improved thickness uniformity

IBM27 citations92

US4916083AApr 10, 1990

High performance sidewall emitter transistor

IBM49 citations92

US4506435AMar 26, 1985

Method for forming recessed isolated regions

IBM45 citations92

US4249968AFeb 10, 1981

Method of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers

IBM43 citations91

US4341009AJul 27, 1982

Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate

IBM32 citations89

US4551906ANov 12, 1985

Method for making self-aligned lateral bipolar transistors

IBM21 citations82

US4847670AJul 11, 1989

High performance sidewall emitter transistor

IBM20 citations81

US4407058AOct 4, 1983

Method of making dense vertical FET's

IBM27 citations81

US4251571AFeb 17, 1981

Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon

IBM26 citations81

US4191603AMar 4, 1980

Making semiconductor structure with improved phosphosilicate glass isolation

IBM29 citations81

US5227333AJul 13, 1993

Local interconnection having a germanium layer

IBM17 citations74

US4403394ASep 13, 1983

Formation of bit lines for ram device

IBM20 citations74

US4654119AMar 31, 1987

Method for making submicron mask openings using sidewall and lift-off techniques

IBM10 citations73

US4394406AJul 19, 1983

Double polysilicon contact structure and process

IBM18 citations72

US4498095AFeb 5, 1985

Semiconductor structure with improved isolation between two layers of polycrystalline silicon

IBM2 citations61

US4437108AMar 13, 1984

Double polysilicon contact structure

IBM1 citations50

SHEPARD JOSEPH F

Patents

Isolation structure using liquid phase oxide deposition

Shallow trench isolation with self aligned PSG layer

Vertical dual gate thin film transistor with self-aligned gates / offset drain

Method of fabricating a semiconductor device with raised diffusions and isolation

Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding

Lithographic image size reduction

Packing density for flash memories

Capacitors with roughened single crystal plates

Method for forming capacitors with roughened single crystal plates

Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon

Method of making a DRAM cell with trench capacitor

Inverse T-gate FET transistor with lightly doped source and drain region

Method of forming an inverse T-gate FET transistor

Mask using lithographic image size reduction

Self-aligned lateral bipolar transistors

Submicron FET structure and method of making

Simplified planarization process for polysilicon filled trenches

Method of making submicron FET structure

Shallow trench isolation with self aligned PSG layer

Method of making thin film transistor with a self-aligned bottom gate using diffusion from a dopant source layer

Method of forming integrated interconnect for very high density DRAMs

Method for forming a DRAM trench cell capacitor having a strap connection

Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding

DRAM cell having raised source, drain and isolation

Method for thinning SOI films having improved thickness uniformity

High performance sidewall emitter transistor

Method for forming recessed isolated regions

Method of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers

Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate

Method for making self-aligned lateral bipolar transistors

High performance sidewall emitter transistor

Method of making dense vertical FET&#39;s

Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon

Making semiconductor structure with improved phosphosilicate glass isolation

Local interconnection having a germanium layer

Formation of bit lines for ram device

Method for making submicron mask openings using sidewall and lift-off techniques

Double polysilicon contact structure and process

Semiconductor structure with improved isolation between two layers of polycrystalline silicon

Double polysilicon contact structure

Method of making dense vertical FET's