Inventor
WORRELL FRANK
US28 patents
⚠️ This page may combine multiple inventors who share the name “WORRELL FRANK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
20 patentsUS5905893AMay 18, 1999
Microprocessor adapted for executing both a non-compressed fixed length instruction set and a compressed variable length instruction set
LSI LOGIC CORP87 citations96
US5896519AApr 20, 1999
Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions
LSI LOGIC CORP59 citations96
US6012138AJan 4, 2000
Dynamically variable length CPU pipeline for efficiently executing two instruction sets
LSI LOGIC CORP24 citations92
US5867681AFeb 2, 1999
Microprocessor having register dependent immediate decompression
LSI LOGIC CORP52 citations92
US5794010AAug 11, 1998
Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor
LSI LOGIC CORP41 citations92
US5774709AJun 30, 1998
Enhanced branch delay slot handling with single exception program counter
LSI LOGIC CORP48 citations92
US5648733AJul 15, 1997
Scan compatible 3-state bus control
LSI LOGIC CORP35 citations92
US7069363B1Jun 27, 2006
On-chip bus
LSI LOGIC CORP12 citations84
US6728816B1Apr 27, 2004
Simple mechanism for guaranteeing in order read data return on a split transaction bus
LSI LOGIC CORP18 citations84
US6412066B2Jun 25, 2002
Microprocessor employing branch instruction to set compression mode
LSI LOGIC CORP14 citations83
US6877082B1Apr 5, 2005
Central processing unit including address generation system and instruction fetch apparatus
LSI LOGIC CORP9 citations74
US5982194ANov 9, 1999
Arithmetic and logic function circuits optimized for datapath layout
LSI LOGIC CORP14 citations74
US5931941AAug 3, 1999
Interface for a modularized computational unit to a CPU
LSI LOGIC CORP9 citations74
US5784634AJul 21, 1998
Pipelined CPU with instruction fetch, execution and write back stages
LSI LOGIC CORP7 citations74
US5729482AMar 17, 1998
Microprocessor shifter using rotation and masking operations
LSI LOGIC CORP16 citations74
US5670900ASep 23, 1997
Mask decoder circuit optimized for data path
LSI LOGIC CORP7 citations74
US6973561B1Dec 6, 2005
Processor pipeline stall based on data register status
LSI LOGIC CORP8 citations69
US6948054B2Sep 20, 2005
Simple branch prediction and misprediction recovery method
LSI LOGIC CORP4 citations63
US6671781B1Dec 30, 2003
Data cache store buffer
LSI LOGIC CORP6 citations63
US6584537B1Jun 24, 2003
Data-cache data-path
LSI LOGIC CORP0 citations49
CAVIUM INC
4 patentsUS9667446B2May 30, 2017
Condition code approach for comparing rule and packet data that are provided in portions
CAVIUM INC9 citations84
US9544402B2Jan 10, 2017
Multi-rule approach to encoding a group of rules
CAVIUM INC8 citations84
US9928193B2Mar 27, 2018
Distributed timer subsystem
CAVIUM INC0 citations51
US9568944B2Feb 14, 2017
Distributed timer subsystem across multiple devices
CAVIUM INC1 citations51
LSI CORP
4 patentsUS7797467B2Sep 14, 2010
Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features
LSI CORP7 citations72
US7681017B2Mar 16, 2010
Pseudo pipeline and pseudo pipelined SDRAM controller
LSI CORP3 citations63
US8046505B2Oct 25, 2011
Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features
LSI CORP2 citations61
US7966431B2Jun 21, 2011
Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features
LSI CORP3 citations61