Inventor · disambiguated record
Eric E. Retter
Also filed as: RETTER ERIC · RETTER ERIC E · RETTER ERIC EUGENE
71 granted patents·1 pending application·2,076 citations·filing 1992–2021
99Inventor score
Top patents by PatentIndex Score
72 records- 0197US7587559B2Systems and methods for memory module power managementIBM·Filed 2006·Granted Sep 8, 2009·63 cites·28 claims
- 0297US5717943AAdvanced parallel array processor (APAP)IBM·Filed 1995·Granted Feb 10, 1998·345 cites·117 claims
- 0396US9684461B1Dynamically adjusting read data return sizes based on memory interface bus utilizationIBM·Filed 2016·Granted Jun 20, 2017·20 cites·17 claims
- 0496US7421598B2Dynamic power management via DIMM read operation limiterIBM·Filed 2005·Granted Sep 2, 2008·69 cites·6 claims
- 0596US5963745AAPAP I/O programmable routerIBM·Filed 1995·Granted Oct 5, 1999·377 cites·14 claims
- 0696US5590345AAdvanced parallel array processor(APAP)IBM·Filed 1992·Granted Dec 31, 1996·300 cites·2 claims
- 0793US8139430B2Power-on initialization and test for a cascade interconnect memory systemBUCHMANN PETER L·Filed 2008·Granted Mar 20, 2012·46 cites·19 claims
- 0893US7493456B2Memory queue with supplemental locations for consecutive addressesIBM·Filed 2006·Granted Feb 17, 2009·33 cites·20 claims
- 0991US9892066B1Dynamically adjusting read data return sizes based on interconnect bus utilizationIBM·Filed 2016·Granted Feb 13, 2018·7 cites·18 claims
- 1091US9436548B2ECC bypass using low latency CE correction with retry select signalGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 6, 2016·12 cites·8 claims
- 1191US9430418B2Synchronization and order detection in a memory systemIBM·Filed 2013·Granted Aug 30, 2016·11 cites·17 claims
- 1291US5710935AAdvanced parallel array processor (APAP)IBM·Filed 1995·Granted Jan 20, 1998·141 cites·10 claims
- 1391US5625836ASIMD/MIMD processing memory element (PME)IBM·Filed 1995·Granted Apr 29, 1997·208 cites·21 claims
- 1489US9146864B2Address mapping including generic bits for universal addressing independent of memory typeIBM·Filed 2013·Granted Sep 29, 2015·12 cites·19 claims
- 1588US9176877B2Provision of early data from a lower level cache memoryIBM·Filed 2013·Granted Nov 3, 2015·10 cites·9 claims
- 1687US9594647B2Synchronization and order detection in a memory systemIBM·Filed 2016·Granted Mar 14, 2017·4 cites·1 claims
- 1787US9318171B2Dual asynchronous and synchronous memory systemIBM·Filed 2014·Granted Apr 19, 2016·8 cites·12 claims
- 1887US9142272B2Dual asynchronous and synchronous memory systemIBM·Filed 2013·Granted Sep 22, 2015·9 cites·8 claims
- 1987US9058260B2Transient condition management utilizing a posted error detection processing protocolIBM·Filed 2013·Granted Jun 16, 2015·8 cites·10 claims
- 2084US9477550B2ECC bypass using low latency CE correction with retry select signalGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 25, 2016·6 cites·13 claims
- 2184US5842031AAdvanced parallel array processor (APAP)IBM·Filed 1995·Granted Nov 24, 1998·95 cites·8 claims
- 2282US8122223B2Access speculation predictor with predictions based on memory region prior requestor tag informationCANTIN JASON F·Filed 2008·Granted Feb 21, 2012·11 cites·23 claims
- 2381US8352806B2System to improve memory failure management and associated methodsIBM·Filed 2008·Granted Jan 8, 2013·12 cites·19 claims
- 2481US6654835B1High bandwidth data transfer employing a multi-mode, shared line bufferIBM·Filed 2000·Granted Nov 25, 2003·21 cites·51 claims
- 2579US9128868B2System for error decoding with retries and associated methodsLASTRAS-MONTANO LUIS A·Filed 2008·Granted Sep 8, 2015·9 cites·20 claims
- 2679US8909874B2Memory reorder queue biasing preceding high latency operationsBRITTAIN MARK A·Filed 2012·Granted Dec 9, 2014·5 cites·14 claims
- 2778US9361240B2Dynamic reservations in a unified request queueIBM·Filed 2013·Granted Jun 7, 2016·4 cites·19 claims
- 2878US8650437B2Computer system and method of protection for the system's marking storeFRY RICHARD E·Filed 2010·Granted Feb 11, 2014·6 cites·19 claims
- 2978US8099570B2Methods, systems, and computer program products for dynamic selective memory mirroringO'CONNOR JAMES A·Filed 2008·Granted Jan 17, 2012·10 cites·14 claims
- 3078US7661008B2Real time clock circuit having an internal clock generatorIBM·Filed 2005·Granted Feb 9, 2010·6 cites·14 claims
- 3177US5617577AAdvanced parallel array processor I/O connectionIBM·Filed 1995·Granted Apr 1, 1997·84 cites·14 claims
- 3276US9378144B2Modification of prefetch depth based on high latency eventIBM·Filed 2013·Granted Jun 28, 2016·3 cites·8 claims
- 3376US8103900B2Implementing enhanced memory reliability using memory scrub operationsFRY RICHARD E·Filed 2009·Granted Jan 24, 2012·8 cites·20 claims
- 3475US6701397B1Pre-arbitration request limiter for an integrated multi-master bus systemIBM·Filed 2000·Granted Mar 2, 2004·16 cites·26 claims
- 3573US6958953B2Real time clock circuit having an internal clock generatorIBM·Filed 2003·Granted Oct 25, 2005·11 cites·11 claims
- 3672US10176125B2Dynamically adjusting read data return sizes based on interconnect bus utilizationIBM·Filed 2017·Granted Jan 8, 2019·1 cites·19 claims
- 3771US9384136B2Modification of prefetch depth based on high latency eventIBM·Filed 2013·Granted Jul 5, 2016·2 cites·19 claims
- 3871US9286220B2Provision of early data from a lower level cache memoryIBM·Filed 2013·Granted Mar 15, 2016·2 cites·6 claims
- 3970US8867304B2Command throttling for multi-channel duty-cycle based memory power managementIBM·Filed 2013·Granted Oct 21, 2014·2 cites·7 claims
- 4069US8996824B2Memory reorder queue biasing preceding high latency operationsIBM·Filed 2013·Granted Mar 31, 2015·2 cites·7 claims
- 4169US8990641B2Selective posted data error detection based on historyIBM·Filed 2012·Granted Mar 24, 2015·2 cites·23 claims
- 4269US8181094B2System to improve error correction using variable latency and associated methodsLASTRAS-MONTANO LUIS A·Filed 2008·Granted May 15, 2012·4 cites·20 claims
- 4369US7380161B2Switching a defective signal line with a spare signal line without shutting down the computer systemIBM·Filed 2005·Granted May 27, 2008·6 cites·8 claims
- 4468US9632954B2Memory queue handling techniques for reducing impact of high-latency memory operationsBRITTAIN MARK A·Filed 2011·Granted Apr 25, 2017·2 cites·28 claims
- 4567US9665346B2Performing arithmetic operations using both large and small floating point valuesIBM·Filed 2014·Granted May 30, 2017·1 cites·25 claims
- 4667US9037811B2Tagging in memory control unit (MCU)IBM·Filed 2013·Granted May 19, 2015·2 cites·17 claims
- 4765US7707452B2Recovering from errors in a data processing systemIBM·Filed 2008·Granted Apr 27, 2010·2 cites·16 claims
- 4864US9384146B2Dynamic reservations in a unified request queueIBM·Filed 2013·Granted Jul 5, 2016·1 cites·8 claims
- 4964US8675444B2Synchronized command throttling for multi-channel duty-cycle based memory power managementDODSON JOHN·Filed 2011·Granted Mar 18, 2014·2 cites·13 claims
- 5063US10649511B2Scalable data collection for system managementIBM·Filed 2019·Granted May 12, 2020·0 cites·15 claims
Showing the top 50 of 72 patent records by PatentIndex Score.
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