Inventor · disambiguated record
Pavel Peleska
Also filed as: PELESKA PAVEL
9 granted patents·7 pending applications·64 citations·filing 1999–2018
86Inventor score
Top patents by PatentIndex Score
16 records- 0191US9946325B2Interprocessor power state transitionsINTEL IP CORP·Filed 2016·Granted Apr 17, 2018·12 cites·20 claims
- 0286US10509762B2Data rate-adaptive data transfer between modems and host platformsINTEL IP CORP·Filed 2018·Granted Dec 17, 2019·5 cites·25 claims
- 0383US10866625B2Data rate adaptive link speed configuration for connection between host processor and modemINTEL CORP·Filed 2018·Granted Dec 15, 2020·4 cites·20 claims
- 0477US10627886B2Interprocessor power state transitionsINTEL IP CORP·Filed 2018·Granted Apr 21, 2020·2 cites·20 claims
- 0561US6959400B2System and method for establishing consistent memory contents in redundant systemsSIEMENS AG·Filed 2002·Granted Oct 25, 2005·10 cites·17 claims
- 0649US10855600B2System, apparatus and method for traffic shaping of data communication via an interconnectINTEL CORP·Filed 2018·Granted Dec 1, 2020·0 cites·18 claims
- 0745US6757766B1Bus system for a highly scalable multiprocessor system and method for transmitting information in the bus systemSIEMENS AG·Filed 1999·Granted Jun 29, 2004·23 cites·19 claims
- 0841US6236549B1Circuit for preventing module damage in integrated circuits which require a plurality of supply voltagesSIEMENS AG·Filed 1999·Granted May 22, 2001·7 cites·1 claims
- 0940US2005229035A1Method for event synchronisation, especially for processors of fault-tolerant systemsPELESKA PAVEL·Filed 2003·Application pending·0 cites
- 1039US2008313413A1Method and Device for Insuring Consistent Memory Contents in Redundant Memory UnitsHUTNER FRANZ·Filed 2004·Application pending·0 cites
- 1138US2006195849A1Method for synchronizing events, particularly for processors of fault-tolerant systemsPELESKA PAVEL·Filed 2003·Application pending·0 cites
- 1238US2004193735A1Method and circuit arrangement for synchronization of synchronously or asynchronously clocked processor unitsFiled 2003·Application pending·0 cites
- 1335US2003041290A1Method for monitoring consistent memory contents in redundant systemsFiled 2002·Application pending·0 cites
- 1434US2006031642A1Circuit arrangement and method of a multiprocessor systemMAENZ MARTIN·Filed 2005·Application pending·0 cites
- 1533US2004177289A1Method and arrangement for detecting and correcting line defectsFiled 2003·Application pending·0 cites
- 1626US6642733B1Apparatus for indentifying defects in electronic assembliesSIEMENS AG·Filed 1999·Granted Nov 4, 2003·1 cites·7 claims
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