Inventor

WAN RAY-LIN

US38 patents

⚠️ This page may combine multiple inventors who share the name “WAN RAY-LIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WAN RAY-LIN

MACRONIX INT CO LTD

Automatic programming algorithm for page mode flash memory with variable programming pulse height and pulse width

Page mode floating gate memory device storing multiple bits per cell

Method and integrated circuit for bit line soft programming (BLISP)

Flash memory device with multiple checkpoint erase suspend logic

Memory cell sense amplifier

Fowler-Nordheim (F-N) tunneling for pre-programming in a floating gate memory device

Page mode program, program verify, read and erase verify for floating gate memory device with low current page buffer

Floating gate memory device and method for terminating a program load cycle upon detecting a predetermined address/data pattern

Method and system for soft programming algorithm

Advanced program verify for page mode flash memory

Technique for reconfiguring a high density memory

Parallel read and verify for floating gate memory device

Four-phase charge pump with lower peak current

Non-volatile integrated circuit having read while write capability using one address register

Bit latch scheme for parallel program verify in floating gate memory device

Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices

Enhanced word line driver to reduce gate capacitance for low voltage applications

Triple well charge pump

Power on reset circuit

Block decoded wordline driver with positive and negative voltage modes

Triple well floating gate memory and operating method with isolated channel program, preprogram and erase processes

Channel FN program/erase recovery scheme

Block decoded wordline driver with positive and negative voltage modes using four terminal MOS transistors

Block-level wordline enablement to reduce negative wordline stress

Low current floating gate programming with bit-by-bit verification

Flash memory erase with controlled band-to-band tunneling current

Memory supporting multiple address protocols

Rapid on chip voltage generation for low power integrated circuits

Low threshold MOS two phase negative charge pump

Address transition detection circuit for a semiconductor memory capable of detecting narrowly spaced address changes

Technique for increasing endurance of integrated circuit memory

Series capacitor charge pump with dynamic biasing

Word line boost circuit

Automatic test process with non-volatile result table store

Output pad precharge circuit for semiconductor devices

Low voltage supply circuit for integrated circuit

ALTERA CORP

Look-ahead asynchronous register set/reset in programmable logic device

MACRONIX INT L CO LTD

Decoded wordline driver with positive and negative voltage modes