Inventor
MCCLINTOCK CAMERON
US55 patents
⚠️ This page may combine multiple inventors who share the name “MCCLINTOCK CAMERON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
49 patentsUS6215326B1Apr 10, 2001
Programmable logic device architecture with super-regions having logic regions and a memory region
ALTERA CORP331 citations99
US5909126AJun 1, 1999
Programmable logic array integrated circuit devices with interleaved logic array blocks
ALTERA CORP133 citations99
US5541530AJul 30, 1996
Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks
ALTERA CORP181 citations99
US5537057AJul 16, 1996
Programmable logic array device with grouped logic regions and three types of conductors
ALTERA CORP326 citations99
US5241224AAug 31, 1993
High-density erasable programmable logic device architecture using multiplexer interconnections
ALTERA CORP178 citations99
US6271679B1Aug 7, 2001
I/O cell configuration for multiple I/O standards
ALTERA CORP103 citations98
US5982195ANov 9, 1999
Programmable logic device architectures
ALTERA CORP114 citations98
US5828229AOct 27, 1998
Programmable logic array integrated circuits
ALTERA CORP185 citations98
US5598109AJan 28, 1997
Programmable logic array device with grouped logic regions and three types of conductors
ALTERA CORP116 citations98
US6605962B2Aug 12, 2003
PLD architecture for flexible placement of IP function blocks
ALTERA CORP27 citations96
US6166559ADec 26, 2000
Redundancy circuitry for logic circuits
ALTERA CORP65 citations96
US5847617ADec 8, 1998
Variable-path-length voltage-controlled oscillator circuit
ALTERA CORP91 citations96
US5614840AMar 25, 1997
Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors
ALTERA CORP62 citations96
US5612642AMar 18, 1997
Power-on reset circuit with hysteresis
ALTERA CORP77 citations96
US5592106AJan 7, 1997
Programmable logic array integrated circuits with interconnection conductors of overlapping extent
ALTERA CORP60 citations96
US5543732AAug 6, 1996
Programmable logic array devices with interconnect lines of various lengths
ALTERA CORP75 citations96
US5384499AJan 24, 1995
High-density erasable programmable logic device architecture using multiplexer interconnections
ALTERA CORP49 citations96
US5144167ASep 1, 1992
Zero power, high impedance TTL-to-CMOS converter
ALTERA CORP60 citations96
US5999016ADec 7, 1999
Architectures for programmable logic devices
ALTERA CORP106 citations95
US6278291B1Aug 21, 2001
Programmable logic array devices with interconnect lines of various lengths
ALTERA CORP28 citations93
US6091258AJul 18, 2000
Redundancy circuitry for logic circuits
ALTERA CORP32 citations93
US6034536AMar 7, 2000
Redundancy circuitry for logic circuits
ALTERA CORP40 citations93
US5963049AOct 5, 1999
Programmable logic array integrated circuit architectures
ALTERA CORP24 citations93
US5900743AMay 4, 1999
Programmable logic array devices with interconnect lines of various lengths
ALTERA CORP18 citations93
US5760624AJun 2, 1998
Power-on reset circuit with hysteresis
ALTERA CORP18 citations93
US5705939AJan 6, 1998
Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors
ALTERA CORP40 citations93
US6661253B1Dec 9, 2003
Passgate structures for use in low-voltage applications
ALTERA CORP29 citations92
US6515508B1Feb 4, 2003
Differential interconnection circuits in programmable logic devices
ALTERA CORP31 citations92
US5821787AOct 13, 1998
Power-on reset circuit with well-defined reassertion voltage
ALTERA CORP28 citations92
US5268598ADec 7, 1993
High-density erasable programmable logic device architecture using multiplexer interconnections
ALTERA CORP33 citations92
US7196542B1Mar 27, 2007
Techniques for providing increased flexibility to input/output banks with respect to supply voltages
ALTERA CORP11 citations84
US7034570B2Apr 25, 2006
I/O cell configuration for multiple I/O standards
ALTERA CORP11 citations84
US6826741B1Nov 30, 2004
Flexible I/O routing resources
ALTERA CORP18 citations84
US6836151B1Dec 28, 2004
I/O cell configuration for multiple I/O standards
ALTERA CORP5 citations74
US6714050B2Mar 30, 2004
I/O cell configuration for multiple I/O standards
ALTERA CORP11 citations74
US6653862B2Nov 25, 2003
Use of dangling partial lines for interfacing in a PLD
ALTERA CORP11 citations74
US5606276AFeb 25, 1997
Method and apparatus for creating a large delay in a pulse in a layout efficient manner
ALTERA CORP16 citations74
US5128565AJul 7, 1992
Sense amplifier with increased speed and reduced power consumption
ALTERA CORP8 citations74
US7584447B2Sep 1, 2009
PLD architecture for flexible placement of IP function blocks
ALTERA CORP3 citations73
US7058920B2Jun 6, 2006
Methods for designing PLD architectures for flexible placement of IP function blocks
ALTERA CORP7 citations73
US6480028B2Nov 12, 2002
Programmable logic device architectures with super-regions having logic regions and memory region
ALTERA CORP5 citations73
US6121790ASep 19, 2000
Programmable logic device with enhanced multiplexing capabilities in interconnect resources
ALTERA CORP6 citations72
US7800405B2Sep 21, 2010
Passgate structures for use in low-voltage applications
ALTERA CORP3 citations63
US7557608B2Jul 7, 2009
Passgate structures for use in low-voltage applications
ALTERA CORP2 citations63
US7119574B1Oct 10, 2006
Passage structures for use in low-voltage applications
ALTERA CORP3 citations63
US6879183B2Apr 12, 2005
Programmable logic device architectures with super-regions having logic regions and a memory region
ALTERA CORP2 citations63
US6859065B2Feb 22, 2005
Use of dangling partial lines for interfacing in a PLD
ALTERA CORP4 citations63
US6396304B2May 28, 2002
Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks
ALTERA CORP4 citations63
US6127846AOct 3, 2000
Programmable logic array devices with interconnect lines of various lengths
ALTERA CORP4 citations63
LEE ANDY L
1 patentShowing the top 50 of 55 patents by PatentIndex Score.