Inventor

PROEBSTING ROBERT J

US114 patents

⚠️ This page may combine multiple inventors who share the name “PROEBSTING ROBERT J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PROEBSTING ROBERT J

INTEGRATED DEVICE TECH

Programmable and electrically configurable latch timing circuit

Merging write cycles by comparing at least a portion of the respective write cycle addresses

Generating a tail current for a differential transistor pair using a capacitive device to project a current flowing through a current source device onto a node having a different voltage than the current source device

Dynamic memory array having write data applied to selected bit line sense amplifiers before sensing to write associated selected memory cells

Hierarchical dynamic memory array architecture using read amplifiers separate from bit line sense amplifiers

Equilibration circuit and method using a pulsed equilibrate signal and a level equilibrate signal

Noise reduction system and method for reducing switching noise in an interface to a large width bus

Integrated circuit random access memory capable of automatic internal refresh of memory array

Intializing memory cells within a dynamic memory array prior to performing internal memory operations

Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle

Methods of controlling memory buffers having tri-port cache arrays therein

DRAM-based CAM cell with shared bitlines

Overvoltage protection circuits that utilize capacitively bootstrapped variable voltages

Highly integrated tri-port memory buffers having fast fall-through capability and methods of operating same

Buffer memory arrays having nonlinear columns for providing parallel data access capability and methods of operating same

Integrated circuit devices having high precision digital delay lines therein

Content addressable memory (CAM) devices having dedicated mask cell sub-arrays therein and methods of operating same

Content addressable memory (CAM) devices having CAM array blocks therein that conserve bit line power during staged compare operations

Noise reduction system and method for reducing switching noise in an interface to a large width bus

Integrated circuit memory devices having partitioned multi-port memory arrays therein for increasing data bandwidth and methods of operating same

TOWNSEND & TOWNSEND & CREW LLP

Method and apparatus for pipelining data in an integrated circuit

Separate set/reset paths for time critical signals

Redundancy scheme for memory circuits

Oscillator receiving variable supply voltage depending on substrate voltage detection

Various embodiments for a low power adaptive charge pump circuit

Method and apparatus for pipelining data in an integrated circuit

Low power liquid-crystal display driver

Self adjusting delay circuit and method for compensating sense amplifier clock timing

High speed low power sense amplifier

(unassigned)

Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD

Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage

Differential sense amplifier circuit

Bit line cross-over layout arrangement

Fast propagation technique in CMOS integrated circuits

Word line straps using two different layers of metal

Power bussing layout for memory circuits

MOSTEK CORP

MOS Random access memory cell with nonvolatile storage

MOSFET buffer for TTL logic input and method of operation

Clock generator and delay stage

GO/NO GO margin test circuit for semiconductor memory

Semiconductor memory cell margin test circuit

Semiconductor memory for use in conjunction with error detection and correction circuit

Current limiting MOS transistor driver circuit

INTERGRAPH CORP

High speed redundant rows and columns for semiconductor memories

Multi-layered integrated circuit package with improved high frequency performance

Low voltage swing output mos circuit for driving an ecl circuit

NAT SEMICONDUCTOR CORP

Speed enhancement technique for CMOS circuits

Speed enhancement technique for CMOS circuits

INTELLECTUAL VENTURES I LLC

Refresh request queuing circuitry

THOMSON COMPONENTS MOSTEK CORP

MOS transistor circuits having matched channel width and length dimensions