Inventor

BLOMGREN JAMES S

US117 patents

⚠️ This page may combine multiple inventors who share the name “BLOMGREN JAMES S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BLOMGREN JAMES S

EXPONENTIAL TECHN INC

Dual-instruction-set architecture CPU with hidden software emulation mode

Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU

Dual-architecture super-scalar pipeline

Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order

Shared register architecture for a dual-instruction-set CPU

Multi-processor DRAM controller that prioritizes row-miss requests to stale banks

Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint register

Emulating operating system calls in an alternate instruction set using a modified code segment descriptor

Bi-planar multi-chip module

Block-based branch prediction using a target finder array storing target sub-addresses

Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor

Stack push/pop tracking and pairing in a pipelined processor

Shared floating-point registers and register port-pairing in a dual-architecture CPU

Translator having segment bounds encoding for storage in a TLB

Splitting a floating-point stack-exchange instruction for merging into surrounding instructions by operand translation

Program watchpoint checking using paging with sub-page validity

Master-slave cache system for instruction and data cache memories

Address tracking and branch resolution in a processor with multiple execution pipelines and instruction stream discontinuities

Emulation of segment bounds checking using paging with sub-page validity

Self-testing multi-processor die with internal compare points

Reduced-modulus address generation using sign-extension and correction

Early instruction-length pre-decode of variable-length instructions in a superscalar processor

INTRINSITY INC

Method and apparatus for TLB memory ordering

Method and apparatus for a 5:2 carry-save-adder (CSA)

Method and apparatus for an enhanced floating point unit with graphics and integer capabilities

Physical realization of dynamic logic using parameterized tile partitioning

Method and apparatus that enforces a regional memory model in hierarchical memory systems

Rounding anticipator for floating point operations

Method and apparatus for a late pipeline enhanced floating point unit

Dynamic adjustment of the clock rate in logic circuits

Method and apparatus for generating clock signals

Method and apparatus for routing 1 of 4 signals

Method and apparatus for two-stage address generation

Method and apparatus for routing 1 of N signals

Method and apparatus for a RAM circuit having N-Nary output interface

Method and apparatus for logic synchronization

Method and apparatus for a logic circuit with constant power consumption

Multiple-state simulation for non-binary logic

Method and apparatus for dynamic partitionable saturating adder/subtractor

1-of-4 multiplier

S3 INC

Debug and video queue for multi-processor chip

Microprocessor with a large cache shared by redundant CPUs for increasing manufacturing yield

Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets

Multiplier with selectable booth encoders for performing 3D graphics interpolations with two multiplies in a single pass through the multiplier

Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register

Dual-instruction-set CPU having shared register for storing data before switching to the alternate instruction set

EVSX INC

Method and apparatus for logic circuit speed detection

Method and apparatus for a N-nary logic circuit using 1 of N signals

Method and apparatus for a N-nary logic circuit using 1 of 4 signals

CHIPS & TECH INC

Microprocessor with operation capture facility