Inventor

ABDALLAH MOHAMMAD

111 patents

⚠️ This page may combine multiple inventors who share the name “ABDALLAH MOHAMMAD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ABDALLAH MOHAMMAD

INTEL CORP

Method and apparatus for efficient vertical SIMD computations

System and method of converting data formats and communicating between execution units

Dual function system and method for shuffling packed data elements

Method for executing multithreaded instructions grouped into blocks

System and method for performing an insert-extract instruction

Method for emulating a guest centralized flag architecture by using a native distributed flag architecture

Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions

Method and apparatus for handling imprecise exceptions

Shared cache structure for temporal and non-temporal instructions

Optimization for 3-D graphic transformation using SIMD computations

Method and apparatus for floating point operations and format conversion operations

Booth multiplier for handling variable width operands

Execution unit for performing shuffle and other operations

Method for populating register view data structure by using register template snapshots

Method for implementing a reduced size register view data structure in a microprocessor

Method for performing dual dispatch of blocks and half blocks

Executing partial-width packed data instructions

Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation

Executing partial-width packed data instructions

Using a plurality of conversion tables to implement an instruction set agnostic runtime architecture

Microprocessor accelerated code optimizer

Method for a delayed branch implementation by using a front end track table

Hardware accelerated conversion system using pattern matching

Systems and methods for accessing a unified translation lookaside buffer

Method for performing dual dispatch of blocks and half blocks

Methods, systems and apparatus for predicting the way of a set associative cache

Instruction sequence buffer to enhance branch prediction efficiency

Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines

Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization

Guest instruction block with near branching and far branching sequence construction to native instruction block

Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines

Method for a delayed branch implementation by using a front end track table

Method for a stage optimized high speed adder

System converter that implements a reordering process through JIT (just in time) optimization that ensures loads do not dispatch ahead of other loads that are to the same address

ABDALLAH MOHAMMAD

Multilevel conversion table cache for translating guest instructions to native instructions

Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines

Mapping of guest instruction block assembled according to branch prediction to translated native conversion block

Instruction sequence buffer to enhance branch prediction efficiency

Guest instruction block with near branching and far branching sequence construction to native instruction block

Single cycle multi-branch prediction including shadow cache for early far branch prediction

Accelerated code optimizer for a multiengine microprocessor

Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor

Guest to native block address mappings and management of native code storage

Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines

AVUDAIYAPPAN KARTHIKEYAN

Systems and methods for accessing a unified translation lookaside buffer

Cache replacement policy

Systems and methods for load canceling in a processor that is connected to an external interconnect fabric

Systems and methods for supporting a plurality of load and store accesses of a cache

SOFT MACHINES INC

Method for populating register view data structure by using register template snapshots

(unassigned)

System and method for performing a MOVHPS-MOVLPS instruction