Inventor

BALMER KEITH

GB70 patents

⚠️ This page may combine multiple inventors who share the name “BALMER KEITH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BALMER KEITH

TEXAS INSTRUMENTS INC

Data processing system with register store/load utilizing data packing/unpacking

Microprocessor with instructions for shuffling and dealing data

Long instruction word controlling plural independent processor operations

Data transfer controller employing differing memory interface protocols dependent upon external input at predetermined time

Synchronized MIMD multi-processing system and method of operation

Three input arithmetic logic unit with shifter and/or mask generator

Synchronized MIMD multi-processing system and method inhibiting instruction fetch at other processors while one processor services an interrupt

Synchronized MIMD multi-processing system and method inhibiting instruction fetch at other processors on write to program counter of one processor

Synchronized MIMD multi-processing system and method inhibiting instruction fetch on memory access stall

Arithmetic logic unit with conditional register source selection

Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor

Register to memory data transfers with field extraction and zero/sign extension based upon size and mode data corresponding to employed address register

Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors

Address generator with controllable modulo power of two addressing capability

Multiple operations employing divided arithmetic logic unit and multiple flags register

Three input arithmetic logic unit with mask generator

Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors

Multi-processor with crossbar link of processors and memories and method of operation

Multi-processor having control over synchronization of processors in mind mode and method of operation

Ones counting circuit, utilizing a matrix of interconnected half-adders, for counting the number of ones in a binary string of image data

Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode

Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation

Sliced addressing multi-processor and method of operation

Data processing apparatus with indirect register file access

Single integrated circuit embodying a risc processor and a digital signal processor

Three input arithmetic logic unit with shifter

System and method of memory access in apparatus having plural processors and plural memories

Reduced area of crossbar and method of operation

Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor

Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section

Plural memory access address generation employing guide table entries forming linked list

Long instruction word controlling plural independent processor operations

Data processor with flexible multiply unit

Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result

Three input arithmetic logic unit with barrel rotator

Rotation register for orthogonal data transformation

Long instruction word controlling plural independent processor operations

Three input arithmetic logic unit capable of performing all possible three operand boolean operations with shifter and/or mask generator

Three input arithmetic logic unit with barrel rotator and mask generator

Long instruction word controlling plural independent processor operations

Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections

Memory store from a selected one of a register pair conditional upon the state of a selected status bit

Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically anded with a third input logically ored with the sum/difference logically anded with an inverse of the third input

Three input arithmetic logic unit with controllable shifter and mask generator

Packed word pair multiply operation forming output including most significant bits of product and other bits of one input

Three input arithmetic logic unit with mask generator

Architecture of transfer processor

Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware

(unassigned)

Long instruction word controlling plural independent processor operations

BALMER KEITH

Switch matrix having integrated crosspoint logic and method of operation