Inventor

ROBERTSON IAIN

GB45 patents

⚠️ This page may combine multiple inventors who share the name “ROBERTSON IAIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROBERTSON IAIN

TEXAS INSTRUMENTS INC

Data transfer controller employing differing memory interface protocols dependent upon external input at predetermined time

Transfer controller with hub and ports architecture

Modular interconnection of network switches

Ring configuration for network switches

Memory configuration cache with multilevel hierarchy least recently used cache entry replacement

Memory access controller utilizing cache memory to store configuration information

Architecture of transfer processor

Flip-flop design

Message passing and blast interrupt from processor

Request queue manager in transfer controller with hub and ports

Data processing apparatus with register file bypass

Effective channel priority processing for transfer controller with hub and ports

Technique for pipelining synchronization to maintain throughput across two asynchronous clock domain boundaries

Low cost alternative to large dual port RAM

Guided transfers with variable stepping

Data transfer clock recovery for legacy systems

Communications interface between clock domains with minimal latency

Using write request queue to prevent bottlenecking on slow ports in transfer controller with hub and ports architecture

Parallel transfer size calculation and annulment determination in transfer controller with hub and ports

Bank conflict avoidance in multi-bank DRAMS with shared sense amplifiers

Data transmission

Maintaining remote queue using two counters in transfer controller with hub and ports

External direct memory access processor interface to centralized transaction processor

Method and apparatus for data transfer employing closed loop of memory nodes

Mask generator usable with addressing schemes in either big endian or little endian format

PC-connectivity for on-chip memory

Peripheral access with synchronization feature

Data transmission

Write allocation counter for transfer controller with hub and ports

Transfer request bus node for transfer controller with hub and ports

Distributed service request system for providing fair arbitration using token passing scheme to resolve collisions

Data transfer clock recovery for legacy systems

Serial burn-in monitor

Packet memory management (PACMAN) scheme

SIEMENS IND SOFTWARE INC

Emulating broadcast in a network on chip

Monitoring processors operating in lockstep

Handling trace data for jumps in program flow

Generation of trace messages including an instruction retirement count and a stall count

Broadcasting event messages in a System on Chip using a crosslinked tree structure

Message monitoring

ULTRASOC TECH LIMITED

Monitoring processors operating in lockstep

Variable address length communication protocol

ULTRASOC TECHNOLOGIES LTD

Integrated circuit security

ORACLE AMERICA INC

System and method to facilitate deterministic testing of data transfers between independent clock domains on a chip

QUARCH TECH LTD

Power supply