Inventor

CHEN PAU-LING

US73 patents

⚠️ This page may combine multiple inventors who share the name “CHEN PAU-LING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN PAU-LING

ADVANCED MICRO DEVICES INC

Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge

Uniform bitline strapping of a non-volatile memory cell

Method of bitline shielding in conjunction with a precharging scheme for nand-based flash memory devices

Auto adjusting window placement scheme for an NROM virtual ground array

Algorithm dynamic reference programming

Method for improving read margin in a flash memory device

Negative pump regulator using MOS capacitor

Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold

Modulated charge pump with uses an analog to digital converter to compensate for supply voltage variations

Erase verify scheme for NAND flash

Scheme for page erase and erase verify in a non-volatile memory array

High-voltage CMOS level shifter

Sidewall NROM and method of manufacture thereof for non-volatile memory cells

Memory system having a program and erase voltage modifier

Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor

Charge pump circuit architecture

Parallel page buffer verify or read of cells on a word line using a signal from a reference cell in a flash memory device

Process for forming isolation slots having immunity to surface inversion

Double boosting scheme for NAND to improve program inhibit characteristics

Register driven means to control programming voltages

Method and system for embedded chip erase verification

Method and apparatus for continuously regulating a charge pump output voltage using a capacitor divider

Optimized biasing scheme for NAND read and hot-carrier write operations

Refresh scheme for dynamic page programming

Staggered bitline strapping of a non-volatile memory cell

Staggered bitline strapping of a non-volatile memory cell

Floating gate capacitor for use in voltage regulators

Bit line biasing method to eliminate program disturbance in a non-volatile memory device and memory device employing the same

Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory

High voltage NMOS pass gate having supply range, area, and speed advantages

High voltage NMOS pass gate for integrated circuit with high voltage generator

High density dram trench capacitor isolation employing double epitaxial layers

Fast bandgap reference circuit for use in a low power supply A/D booster

System for programming memory cells

System for erasing a memory cell

Methods and apparatus to perform high voltage electrical rule check of MOS circuit design

Supply voltage-independent reference voltage circuit

Precharging scheme for reading a memory cell

High voltage NMOS pass gate for integrated circuit with high voltage generator and flash non-volatile memory device having the pass gate

Method and system for defining a redundancy window around a particular column in a memory array

Buffer driver circuit for producing a fast, stable, and accurate reference voltage

Method and low-power circuits used to generate accurate drain voltage for flash memory core cells in read mode

Method and low-power circuits used to generate accurate boosted wordline voltage for flash memory core cells in read mode

Fast, accurate and low power supply voltage booster using A/D converter

High voltage NMOS pass gate having supply range, area, and speed advantages

Erase verify mode to evaluate negative Vt&#39;s

FASL LLC

Non-volatile memory read circuit with end of life simulation

Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference

I/O based column redundancy for virtual ground with 2-bit cell flash memory

SPANSION LLC

Multi bit program algorithm

Erase verify mode to evaluate negative Vt's