Inventor
LEE SHYH-DAR
TW23 patents
⚠️ This page may combine multiple inventors who share the name “LEE SHYH-DAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SILICON INTEGRATED SYS CORP
18 patentsUS6696222B2Feb 24, 2004
Dual damascene process using metal hard mask
SILICON INTEGRATED SYS CORP101 citations98
US6521523B2Feb 18, 2003
Method for forming selective protection layers on copper interconnects
SILICON INTEGRATED SYS CORP51 citations92
US6495448B1Dec 17, 2002
Dual damascene process
SILICON INTEGRATED SYS CORP38 citations92
US6492226B1Dec 10, 2002
Method for forming a metal capacitor in a damascene process
SILICON INTEGRATED SYS CORP27 citations92
US6483142B1Nov 19, 2002
Dual damascene structure having capacitors
SILICON INTEGRATED SYS CORP22 citations92
US6391713B1May 21, 2002
Method for forming a dual damascene structure having capacitors
SILICON INTEGRATED SYS CORP22 citations92
US6338999B1Jan 15, 2002
Method for forming metal capacitors with a damascene process
SILICON INTEGRATED SYS CORP21 citations92
US6649512B1Nov 18, 2003
Method for improving adhesion of a low k dielectric to a barrier layer
SILICON INTEGRATED SYS CORP13 citations84
US6503835B1Jan 7, 2003
Method of making an organic copper diffusion barrier layer
SILICON INTEGRATED SYS CORP13 citations84
US6358792B1Mar 19, 2002
Method for fabricating metal capacitor
SILICON INTEGRATED SYS CORP15 citations84
US6410386B1Jun 25, 2002
Method for forming a metal capacitor in a damascene process
SILICON INTEGRATED SYS CORP20 citations81
US6495877B1Dec 17, 2002
Metal capacitors with damascene structures and method for forming the same
SILICON INTEGRATED SYS CORP13 citations74
US6512260B2Jan 28, 2003
Metal capacitor in damascene structures
SILICON INTEGRATED SYS CORP8 citations71
US6548409B1Apr 15, 2003
Method of reducing micro-scratches during tungsten CMP
SILICON INTEGRATED SYS CORP7 citations66
US6603167B2Aug 5, 2003
Capacitor with lower electrode located at the same level as an interconnect line
SILICON INTEGRATED SYS CORP6 citations63
US6593225B1Jul 15, 2003
Method of forming a stacked dielectric layer on a semiconductor substrate having metal patterns
SILICON INTEGRATED SYS CORP3 citations63
US6514815B2Feb 4, 2003
Method for fabricating polysilicon capacitor
SILICON INTEGRATED SYS CORP2 citations63
US6504205B1Jan 7, 2003
Metal capacitors with damascene structures
SILICON INTEGRATED SYS CORP6 citations63
IND TECH RES INST
3 patentsUS6472306B1Oct 29, 2002
Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer
IND TECH RES INST96 citations96
US6242361B1Jun 5, 2001
Plasma treatment to improve DUV photoresist process
IND TECH RES INST14 citations73
US6376392B1Apr 23, 2002
PECVD process for ULSI ARL
IND TECH RES INST12 citations72