Inventor

MOTOMURA MASATO

JP41 patents

⚠️ This page may combine multiple inventors who share the name “MOTOMURA MASATO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOTOMURA MASATO

NEC CORP

Line buffer type semiconductor memory device capable of direct prefetch and restore operations

Coprocessor-integrated packet-type memory LSI, packet-type memory/coprocessor bus, and control method thereof

Programmable logic IC having memories for previously storing a plurality of configuration data and a method of reconfigurating same

Multithreaded processor which dynamically discriminates a parallel execution and a sequential execution of threads

Memory integrated circuit and main memory and graphics memory systems applying the above

Array type processor with state transition controller identifying switch configuration and processing element instruction address

Programmable device with an array of programmable cells and interconnection network

Parallel processor for executing plural thread program in parallel using virtual thread numbers

Data holding circuit having backup function

Multiple line buffer type memory LSI

Programmable device

Superscalar processor with forward map buffer in multiple instruction parallel issue/execution management system

Superscalar processor with parallel issue and execution device having forward map of operand and instruction dependencies

Memory LSI with arithmetic logic processing capability, main memory system using the same, and method of controlling main memory system

Microprocessor having register file

String collating system for searching for character string of arbitrary length within a given distance from reference string

Data processing apparatus and method for generating the data of an object program for a parallel operation apparatus

Motion picture coder and system for controlling the same

Programmable logic LSI

Processor having array of processing elements whose individual operations and mutual connections are variable

Base cell and two-dimensional array of base cells for programmable logic LSI

Address generating and decoding device and method with increased decoding speed

Operation device and operation method for discrete cosine transform and inverse discrete cosine transform

Address generating and decoding apparatus with high operation speed

Data holding circuit having backup function

Processing-function-provided packet-type memory system and method for controlling the same

Semiconductor static random access memory device having previously equalizable memory cells

High-speed memory system

Plural line buffer type memory LSI

Data processing system for debugging utilizing halts in a parallel device

Information processing apparatus and method for using reconfigurable device

Array—type computer processor with reduced instruction storage

NEC ELECTRONICS CORP

Stream processor and information processing apparatus

Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix

Array-type computer processor

TOI TAKAO

Reconfigurable device

Behavioral synthesis apparatus, behavioral synthesis method, and computer readable recording medium

TOKYO INST TECH

Neural network circuit and neural network integrated circuit

HITACHI LTD

Apparatus and method for fully parallelized simulated annealing using a self-action parameter

FUJII TARO

Array-type processor having plural processor elements controlled by a state control unit

RENESAS ELECTRONICS CORP

Switch coupled function blocks with additional direct coupling and internal data passing from input to output to facilitate more switched inputs to second block