Inventor

LI XIAO-YU

US62 patents

⚠️ This page may combine multiple inventors who share the name “LI XIAO-YU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LI XIAO-YU

ADVANCED MICRO DEVICES INC

Process for fabricating a high-endurance non-volatile memory device

Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide

Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate

Method of forming multiple gate oxide thicknesses on a wafer substrate

EEPROM having stacked dielectric to increase programming speed

Method for fabricating a high-density and high-reliability EEPROM device

Method of selectively annealing damaged doped regions

Method of programming and erasing an EEPROM device under an elevated temperature and apparatus thereof

Method and apparatus incorporating nitrogen selectively for differential oxide growth

Method to incorporate, and a device having, oxide enhancement dopants using gas immersion laser doping (GILD) for selectively growing an oxide layer

Vpp only scalable EEPROM memory cell having transistors with thin tunnel gate oxide

STI punch-through defects and stress reduction by high temperature oxide reflow process

Semiconductor device having a multi-layer metal interconnect structure

Method for annealing damaged semiconductor regions allowing for enhanced oxide growth

VANTIS CORP

Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect

Method for sorting semiconductor devices having a plurality of non-volatile memory cells

Triple-well EEPROM cell using P-well for tunneling across a channel

Non-volatile memory device having a high-reliability composite insulation layer

EEPROM cell using P-well for tunneling across a channel

Avalanche injection EEPROM memory cell with P-type control gate

EEPROM cell with tunneling at separate edge and channel regions

Boron doped silicon capacitor plate

Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide

EEPROM cell with field-edgeless tunnel window using shallow trench isolation process

Two transistor EEPROM cell using P-well for tunneling across a channel

EEPROM cell with tunneling across entire separated channels

Two transistor EEPROM cell

AMAZON TECH INC

Equipment rack power reduction using virtual machine instance migration

Capacity-independent demand assessment

Placement of inventory in a materials handling facility

Method and system for inventory placement according to expected item picking rates

Management of demand for virtual computing resources

Management of demand for virtual computing resources

XILINX INC

Increased usable programmable device dice

Method for monitoring and improving integrated circuit fabrication using FPGAs

Method and apparatus for tracking interposer dies in a silicon stacked interconnect technology (SSIT) product

Semiconductor package having IC dice and voltage tuners

Method and circuits for localizing defective interconnect resources in programmable logic devices

Markov decision process based recipe generation for multi-chip apparatus

LATTICE SEMICONDUCTOR CORP

Reduction of mechanical stress in shallow trench isolation process

Stacked tunneling dielectric technology for improving data retention of EEPROM cell

EEPROM cell with self-aligned tunneling window

Optimization of S/D annealing to minimize S/D shorts in memory array

CHEN MAOMAO

Allocating regional inventory to reduce out-of-stock costs

RAFF PAUL

Cost-based fulfillment tie-breaking

BELYI DMITRIY

Systems and methods for allocating inventory in a fulfillment network

ANTONY FELIX F

Method and system for inventory placement according to expected item picking rates

LI XIAO YU

Resource planning for computing

Yunes Jeffrey Michael

Non-binding placement of inventory in a materials handling facility

IBM

Shape-based code comparisons