Inventor

CHEUNG ROBIN W

US47 patents

⚠️ This page may combine multiple inventors who share the name “CHEUNG ROBIN W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEUNG ROBIN W

ADVANCED MICRO DEVICES INC

Apparatus and method of encapsulated copper (Cu) Interconnect formation

Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and high performance IC

Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance

Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS

Electropolishing copper film to enhance CMP throughput

Pulse electroplating copper or copper alloys

Method of forming high density capping layers for copper interconnects with improved adhesion

Method of encapsulated copper (Cu) interconnect formation

Wire bonding CU interconnects

Metallized interconnection structure and method of making the same

Manufacturing capping layer for the fabrication of cobalt salicide structures

Advanced copper interconnect system that is compatible with existing IC wire bonding technology

Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC application

Tunneling technology for reducing intra-conductive layer capacitance

Landing pad technology doubled up as local interconnect and borderless contact for deep sub-half micrometer IC application

Layered low dielectric constant technology

Process for forming stable local interconnect/active area silicide structure VLSI applications

High density capping layers with improved adhesion to copper interconnects

Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS

Low RC interconnection

Eliminating metal extrusions by controlling the liner deposition temperature

Layered low dielectric constant technology

Method to prevent formation of defects during multilayer interconnect processing

Pseudo-low dielectric constant technology

Method for measuring the size of vias

Plugged poly silicon resistor load for static random access memory cells

Integrated circuit structure having intermediate metal silicide layer

Making a low resistance three layered contact for silicon devices

Metallization sidewall passivation technology for deep sub-half micrometer IC applications

Integrated circuit structure having intermediate metal silicide layer and method of making same

Low resistance metal contact for silicon devices

Metallized interconnection structure

Method of forming reliable capped copper interconnects/with high etch selectivity to capping layer

Method of enhanced silicide layer for advanced metal diffusion barrier layer application

Ultra-low temperature Al fill for sub-0.25 μm generation of ICs using an Al-Ge-Cu alloy

Tunneling technology for reducing intra-conductive layer capacitance

Low cost solution to high aspect ratio contact/via adhesion layer application for deep sub-half micrometer back-end-of line technology

Stable local interconnect/active area silicide structure for VLSI applications

Nitride-less process for VLSI circuit device isolation

Selective metal via plug growth technology for deep sub-micrometer ULSI

Stable high density RAM

Selective metal via plug growth technology for deep sub-micrometer ULSI

APPLIED MATERIALS INC

Semiconductor device interconnect fabricating techniques

Method and apparatus for capturing and using design intent in an integrated circuit fabrication process

AMD

Copper/low dielectric interconnect formation with reduced electromigration

ADVANCED MICRO DEVICS INC

Low RC interconnection

APPLE INC

Isolation structures in film-based image sensors