Inventor
MOLSON PHILIPPE
US25 patents
⚠️ This page may combine multiple inventors who share the name “MOLSON PHILIPPE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
20 patentsUS6634009B1Oct 14, 2003
Interleaver-deinterleaver megacore
ALTERA CORP51 citations96
US7143368B1Nov 28, 2006
DSP design system level power estimation
ALTERA CORP45 citations94
US9684615B1Jun 20, 2017
Apparatus and methods for multiple-channel direct memory access
ALTERA CORP22 citations93
US7480603B1Jan 20, 2009
Finite impulse response (FIR) filter compiler
ALTERA CORP18 citations92
US7318014B1Jan 8, 2008
Bit accurate hardware simulation in system level simulators
ALTERA CORP22 citations92
US7089173B1Aug 8, 2006
Hardware opencore evaluation
ALTERA CORP17 citations92
US9053093B1Jun 9, 2015
Modular direct memory access system
ALTERA CORP26 citations91
US7873953B1Jan 18, 2011
High-level language code sequence optimization for implementing programmable chip designs
ALTERA CORP14 citations89
US7991606B1Aug 2, 2011
Embedded logic analyzer functionality for system level environments
ALTERA CORP23 citations88
US9257987B1Feb 9, 2016
Partial reconfiguration using configuration transaction layer packets
ALTERA CORP10 citations84
US7676355B1Mar 9, 2010
Method and apparatus for providing protected intellectual property
ALTERA CORP8 citations84
US7509246B1Mar 24, 2009
System level simulation models for hardware modules
ALTERA CORP13 citations84
US7360189B1Apr 15, 2008
Method and apparatus for enabling waveform display in a system design model
ALTERA CORP11 citations84
US7110927B1Sep 19, 2006
Finite impulse response (FIR) filter compiler
ALTERA CORP16 citations84
US7882457B1Feb 1, 2011
DSP design system level power estimation
ALTERA CORP7 citations82
US9552323B1Jan 24, 2017
High-speed peripheral component interconnect (PCIe) input-output devices with receive buffer management circuitry
ALTERA CORP11 citations79
US7181384B1Feb 20, 2007
Method and apparatus for simulating a hybrid system with registered and concurrent nodes
ALTERA CORP9 citations72
US8661396B1Feb 25, 2014
DSP design system level power estimation
ALTERA CORP1 citations60
US7865347B1Jan 4, 2011
Finite impulse response (FIR) filter compiler for estimating cost of implementing a filter
ALTERA CORP0 citations52
US9329847B1May 3, 2016
High-level language code sequence optimization for implementing programmable chip designs
ALTERA CORP0 citations49