Inventor

CHITTIPEDDI SAILESH

US64 patents

⚠️ This page may combine multiple inventors who share the name “CHITTIPEDDI SAILESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHITTIPEDDI SAILESH

LUCENT TECHNOLOGIES INC

Bond pad design for integrated circuits

Process for forming gate oxides possessing different thicknesses on a semiconductor substrate

Silicon IC contacts using composite TiN barrier layer

Integrated circuit with active devices under bond pads

Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology

Bond pad design for integrated circuits

Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein

Transistor fabrication method

Method of forming a multi-layered dual-polysilicon structure

In-line non-contact depletion capacitance measurement method and apparatus

Bond pad for a flip chip package, and method of forming the same

Bond pad for a flip-chip package

Integrated circuit processing utilizing microwave radiation

Integrated circuit with twin tub

Method for forming shallow trench isolation structures

Method of despositing an aluminum-rich layer

Method and system for evaluating technology transfer value

Silicon-on-insulator (SOI) semiconductor structure with additional trench including a conductive layer

Method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein

Process for forming isolation regions in an integrated circuit

Process for forming integrated capacitors

Method for depositing metal

AGERE SYST GUARDIAN CORP

Process for forming a dual damascene bond pad structure over active circuitry

Electrostatic discharge protection device with monolithically formed resistor-capacitor portion

Distributed communications system for reducing equipment down-time

Method for forming trench capacitors in SOI substrates

Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers

Barrier for copper metallization

Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit

Technique for reducing dishing in Cu-based interconnects

Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit

Transistor fabrication method

Barrier for copper metallization

Method for making a merged contact window in a transistor to electrically connect the gate to either the source or the drain

Method for reducing dishing related issues during the formation of shallow trench isolation structures

AGERE SYSTEMS INC

Wire bonding method for copper interconnects in semiconductor devices

Dual damascene bond pad structure for lowering stress and allowing circuitry under pads

CMOS vertical replacement gate (VRG) transistors

Method for concurrently forming an ESD protection device and a shallow trench isolation region

Wire bonding to copper

Solder bump structure for flip chip semiconductor devices and method of manufacture therefore

Integrated circuit including ESD circuits for a multi-chip module and a method therefor

Integrated circuit with a trench capacitor structure and method of manufacture

Method of forming a semiconductor device

Trench capacitors in SOI substrates

Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers

AT & T BELL LAB

Silicide formation on polysilicon

Transistor fabrication method

Method of fabricating an integrated circuit interconnection

AT & T CORP

Integrated circuit fabrication with a raised feature as mask