Inventor
BROWNSCHEIDLE JEFFREY C
US18 patents
Patents
18 patentsUS9367322B1Jun 14, 2016
Age based fast instruction issue
IBM18 citations92
US9389870B1Jul 12, 2016
Age based fast instruction issue
IBM3 citations72
US10942745B2Mar 9, 2021
Fast multi-width instruction issue in parallel slice processor
IBM0 citations62
US10719056B2Jul 21, 2020
Merging status and control data in a reservation station
IBM1 citations62
US10776122B2Sep 15, 2020
Prioritization protocols of conditional branch instructions
IBM1 citations59
US11150909B2Oct 19, 2021
Energy efficient source operand issue
IBM0 citations51
US10120693B2Nov 6, 2018
Fast multi-width instruction issue in parallel slice processor
IBM1 citations51
US10078516B2Sep 18, 2018
Techniques to wake-up dependent instructions for back-to-back issue in a microprocessor
IBM0 citations51
US10031757B2Jul 24, 2018
Operation of a multi-slice processor implementing a mechanism to overcome a system hang
IBM0 citations51
US9996359B2Jun 12, 2018
Fast multi-width instruction issue in parallel slice processor
IBM0 citations51
US9983879B2May 29, 2018
Operation of a multi-slice processor implementing dynamic switching of instruction issuance order
IBM1 citations51
US9971600B2May 15, 2018
Techniques to wake-up dependent instructions for back-to-back issue in a microprocessor
IBM1 citations51
US9965286B2May 8, 2018
Age based fast instruction issue
IBM0 citations51
US9880850B2Jan 30, 2018
Age based fast instruction issue
IBM0 citations51
US9870231B2Jan 16, 2018
Age based fast instruction issue
IBM0 citations51
US10740107B2Aug 11, 2020
Operation of a multi-slice processor implementing load-hit-store handling
IBM0 citations41
US10445100B2Oct 15, 2019
Broadcasting messages between execution slices for issued instructions indicating when execution results are ready
IBM0 citations41
US10318294B2Jun 11, 2019
Operation of a multi-slice processor implementing dependency accumulation instruction sequencing
IBM0 citations37