Inventor
JEGANATHAN DHIVYA
US19 patents
Patents
19 patentsUS9985655B2May 29, 2018
Generating ECC values for byte-write capable registers
IBM6 citations83
US9985656B2May 29, 2018
Generating ECC values for byte-write capable registers
IBM7 citations83
US10176038B2Jan 8, 2019
Partial ECC mechanism for a byte-write capable register
IBM2 citations72
US9921833B2Mar 20, 2018
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
IBM3 citations72
US9639418B2May 2, 2017
Parity protection of a register
IBM4 citations72
US9959123B2May 1, 2018
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor
IBM2 citations71
US11086630B1Aug 10, 2021
Finish exception handling of an instruction completion table
IBM3 citations69
US10719056B2Jul 21, 2020
Merging status and control data in a reservation station
IBM1 citations62
US11327757B2May 10, 2022
Processor providing intelligent management of values buffered in overlaid architected and non-architected register files
IBM0 citations61
US11775337B2Oct 3, 2023
Prioritization of threads in a simultaneous multithreading processor core
IBM0 citations51
US10649779B2May 12, 2020
Variable latency pipe for interleaving instruction tags in a microprocessor
IBM0 citations51
US10613868B2Apr 7, 2020
Variable latency pipe for interleaving instruction tags in a microprocessor
IBM0 citations51
US10489253B2Nov 26, 2019
On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor
IBM0 citations51
US10031757B2Jul 24, 2018
Operation of a multi-slice processor implementing a mechanism to overcome a system hang
IBM0 citations51
US9983879B2May 29, 2018
Operation of a multi-slice processor implementing dynamic switching of instruction issuance order
IBM1 citations51
US9928073B2Mar 27, 2018
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
IBM0 citations51
US9858078B2Jan 2, 2018
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor
IBM0 citations50
US10445100B2Oct 15, 2019
Broadcasting messages between execution slices for issued instructions indicating when execution results are ready
IBM0 citations41
US9766975B2Sep 19, 2017
Partial ECC handling for a byte-write capable register
IBM0 citations41