Inventor

HIRATANI MASAHIKO

JP39 patents

⚠️ This page may combine multiple inventors who share the name “HIRATANI MASAHIKO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HIRATANI MASAHIKO

HITACHI LTD

Method of manufacturing a semiconductor integrated circuit

Semiconductor integrated circuit and its manufacturing method

Solid state lithium battery

Semiconductor device capacitor with high permittivity tantalum pentoxide/niobium pentoxide dielectric

Method of manufacturing semiconductor devices utilizing underlayer-dependency of deposition of capacitor electrode film, and semiconductor device

Method of manufacturing semiconductor devices utilizing underlayer-dependency of deposition of capacitor electrode film, and semiconductor device

Superconducting field effect transistor with increased channel length

Method of forming weak-link josephson junction, and superconducting device employing the junction

Method of forming a semiconductor device including a capacitor with tantalum oxide (Ta2O5)

Semiconductor device and method of manufacturing thereof

Method of forming a capacitor in a semiconductor integrated circuit device using a metal silicon nitride layer to protect an underlying metal silicide layer from oxidation during subsequent processing steps

Method of manufacturing semiconductor devices utilizing underlayer-dependency of deposition of capacitor electrode film, and semiconductor device

Production of semiconductor integrated circuit

Semiconductor device having a capacitor structure including a self-alignment deposition preventing film

Capacitor structure and a semiconductor device with a first metal layer, a second metal silicide layer formed over the first metal layer and a second metal layer formed over the second metal silicide layer

Semiconductor integrated circuit device and the method of producing the same

Superconductive switching element with semiconductor channel

Bi-layer oxide ferroelectrics

Semiconductor device and its manufacture

Superconducting composition comprising ln-th-cu-o, wherein ln is pr, nd, pm, sm, eu, gd, er or mixtures thereof

Method for making semiconductor integrated circuits

Method of forming a semiconductor device with a capacitor including a polycrystalline tantalum oxide film dielectric

Semiconductor integrated circuits and fabricating method thereof

RENESAS TECH CORP

Fabrication method for semiconductor integrated devices

Semiconductor device having plural dram memory cells and a logic circuit

Semiconductor device

Semiconductor device and manufacturing method thereof

Fabrication method for semiconductor integrated devices

Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same

Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same

Production of semiconductor integrated circuit

Capacitive electrode having semiconductor layers with an interface of separated grain boundaries

Method for manufacturing a ruthenium film for a semiconductor device

Method of making a memory structure having a multilayered contact and a storage capacitor with a composite dielectric layer of crystalized niobium pentoxide and tantalum pentoxide films

Capacitive electrode having semiconductor layers with an interface of separated grain boundaries

Semiconductor device and manufacturing method thereof

AKIYAMA SATORU

Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same

RENESAS TECHONOLOGY CORP

Fabricating method of semiconductor integrated circuits

RENESAS ELECTRONICS CORP

Capacitive electrode having semiconductor layers with an interface of separated grain boundaries