Inventor
CARGNONI ROBERT ALAN
US36 patents
⚠️ This page may combine multiple inventors who share the name “CARGNONI ROBERT ALAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
35 patentsUS6748501B2Jun 8, 2004
Microprocessor reservation mechanism for a hashed address system
IBM59 citations96
US7272664B2Sep 18, 2007
Cross partition sharing of state information
IBM26 citations93
US7047320B2May 16, 2006
Data processing system providing hardware acceleration of input/output (I/O) communication
IBM40 citations93
US6996679B2Feb 7, 2006
Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members
IBM46 citations93
US6981083B2Dec 27, 2005
Processor virtualization mechanism via an enhanced restoration of hard architected states
IBM32 citations93
US6976148B2Dec 13, 2005
Acceleration of input/output (I/O) communication through improved address translation
IBM23 citations93
US6950892B2Sep 27, 2005
Method and system for managing distributed arbitration for multicycle data transfer requests
IBM29 citations93
US7272773B2Sep 18, 2007
Cache directory array recovery mechanism to support special ECC stuck bit matrix
IBM46 citations92
US7069494B2Jun 27, 2006
Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism
IBM48 citations92
US6606666B1Aug 12, 2003
Method and system for controlling information flow between a producer and a buffer in a high frequency digital system
IBM42 citations92
US7055003B2May 30, 2006
Data cache scrub mechanism for large L2/L3 data cache structures
IBM29 citations89
US5835946ANov 10, 1998
High performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizations
IBM42 citations89
US7849298B2Dec 7, 2010
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states
IBM10 citations84
US7360067B2Apr 15, 2008
Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network
IBM9 citations84
US7305526B2Dec 4, 2007
Method, system, and program for transferring data directed to virtual memory addresses to a device memory
IBM13 citations84
US7089364B2Aug 8, 2006
System and method to stall dispatch of gathered store operations in a store queue using a timer
IBM11 citations84
US6604145B1Aug 5, 2003
Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer and a shared data path
IBM16 citations83
US6598086B1Jul 22, 2003
Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer
IBM15 citations83
US7493417B2Feb 17, 2009
Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system
IBM7 citations74
US7117319B2Oct 3, 2006
Managing processor architected state upon an interrupt
IBM9 citations74
US7103721B2Sep 5, 2006
Cache allocation mechanism for biasing subsequent allocations based upon cache directory state
IBM7 citations74
US6983347B2Jan 3, 2006
Dynamically managing saved processor soft states
IBM8 citations74
US7783842B2Aug 24, 2010
Cache coherent I/O communication
IBM6 citations63
US7493478B2Feb 17, 2009
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states
IBM5 citations63
US7359932B2Apr 15, 2008
Method and data processing system for microprocessor communication in a cluster-based multi-processor system
IBM2 citations63
US7356568B2Apr 8, 2008
Method, processing unit and data processing system for microprocessor communication in a multi-processor system
IBM5 citations63
US7039832B2May 2, 2006
Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems
IBM3 citations63
US6477637B1Nov 5, 2002
Method and apparatus for transporting store requests between functional units within a processor
IBM6 citations63
US6601105B1Jul 29, 2003
Method and system for controlling information flow between a producer and multiple buffers in a high frequency digital system
IBM3 citations62
US6490653B1Dec 3, 2002
Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system
IBM4 citations62
US7818364B2Oct 19, 2010
Method and data processing system for microprocessor communication in a cluster-based multi-processor system
IBM0 citations52
US7734877B2Jun 8, 2010
Method and data processing system for processor-to-processor communication in a clustered multi-processor system
IBM0 citations52
US7698373B2Apr 13, 2010
Method, processing unit and data processing system for microprocessor communication in a multi-processor system
IBM0 citations52
US7055002B2May 30, 2006
Integrated purge store mechanism to flush L2/L3 cache structure for improved reliabity and serviceability
IBM1 citations52
US12204832B2Jan 21, 2025
Logical clock connection in an integrated circuit design
IBM0 citations49